Stephan Kassenetter

According to our database1, Stephan Kassenetter authored at least 3 papers between 2012 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2013
Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 65nm 4MB embedded flash macro for automotive achieving a read throughput of 5.7GB/s and a write throughput of 1.4MB/s.
Proceedings of the ESSCIRC 2013, 2013

2012
Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012


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