Doris Schmitt-Landsiedel

Affiliations:
  • Technical University Munich, Germany


According to our database1, Doris Schmitt-Landsiedel authored at least 92 papers between 1990 and 2017.

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Bibliography

2017
Emulation of an ASIC power and temperature monitoring system (eTPMon) for FPGA prototyping.
Microprocess. Microsystems, 2017

A 92.1% efficient DC-DC converter for ultra-low power microcontrollers with fast wake-up.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Scanning Microwave Microscopy for Electronic Device Analysis on Nanometre Scale.
Microelectron. Reliab., 2016

A 2 GHz 244 fs-Resolution 1.2 ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016

Dark silicon management: an integrated and coordinated cross-layer approach.
it Inf. Technol., 2016

2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Towards Logic-In-Memory circuits using 3D-integrated Nanomagnetic logic.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016

In situ measurement of aging-induced performance degradation in digital circuits.
Proceedings of the 21th IEEE European Test Symposium, 2016

A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Emulation of an ASIC power and temperature monitor system for FPGA prototyping.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

A 13.56MHz class e power amplifier for inductively coupled DC supply with 95% power added efficiency (PAE).
Proceedings of the 2015 International EURASIP Workshop on RFID Technology, 2015

Modelling and simulation of nanomagnetic logic with cadence virtuoso using Verilog-A.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Slope only sense amplifier with 4.5ns sense delay for 8Mbit memory sector, employing in situ current monitoring with 66% write speed improvement in 40nm embedded flash for automotive.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A compact model for NBTI degradation and recovery under use-profile variations and its application to aging analysis of digital integrated circuits.
Microelectron. Reliab., 2014

Resilience and yield of flip-flops in future CMOS technologies under process variations and aging.
IET Circuits Devices Syst., 2014

Emulated ASIC Power and Temperature Monitor System for FPGA Prototyping of an Invasive MPSoC Computing Architecture.
CoRR, 2014

Power efficient digital IC design for a medical application with high reliability requirements.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

From an analytic NBTI device model to reliability assessment of complex digital circuits.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

2013
Reliability monitoring of digital circuits by in situ timing measurement.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Time-differential sense amplifier for sub-80mV bitline voltage embedded STT-MRAM in 40nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Nanomagnetic logic clocked in the MHz regime.
Proceedings of the European Solid-State Device Research Conference, 2013

A 65nm 4MB embedded flash macro for automotive achieving a read throughput of 5.7GB/s and a write throughput of 1.4MB/s.
Proceedings of the ESSCIRC 2013, 2013

2012
On-Line Supply voltage Scaling Based on <i>in situ</i> Delay Monitoring to Adapt for Pvta variations.
J. Circuits Syst. Comput., 2012

Bitline-capacitance-cancelation sensing scheme with 11ns read latency and maximum read throughput of 2.9GB/s in 65nm embedded flash for automotive.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
DRAM Yield Analysis and Optimization by a Statistical Design Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Reducing impact of degradation on analog circuits by chopper stabilization and autozeroing.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

An aging suppression and calibration approach for differential amplifiers in advanced CMOS technologies.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

An analog perspective on device reliability in 32nm high-κ metal gate technology.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Invasive Computing: An Overview.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010
Reliability assessment of voltage controlled oscillators in 32nm high-κ metal gate technology.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
Adaptive circuit block model for power supply noise analysis of low power system-on-chip.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

Field-coupled nanomagnets for interconnect-free nonvolatile computing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Adder Circuits with Transistors using Independently Controlled Gates.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Robust Synchronized 2N2P LC Oscillator with a Shut-down Mode for Adiabatic Logic Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Design of Low-Voltage Bandgap Reference Circuits in Multi-Gate CMOS Technologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Fast stability analysis of large-scale SRAM arrays and the impact of NBTI degradation.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

Architectural assessment of design techniques to improve speed and robustness in embedded microprocessors.
Proceedings of the 46th Design Automation Conference, 2009

2008
A Configurable High-Side/Low-Side Driver With Fast and Equalized Switching Delay.
IEEE J. Solid State Circuits, 2008

A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion.
IEEE J. Solid State Circuits, 2008

Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

A Design Space Comparison of 6T and 8T SRAM Core-Cells.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Efficient High-Speed Interface Verification and Fault Analysis.
Proceedings of the 2008 IEEE International Test Conference, 2008

90nm 4.7ps-Resolution 0.7-LSB Single-Shot Precision and 19pJ-per-Shot Local Passive Interpolation Time-to-Digital Converter with On-Chip Characterization.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
RF ESD protection strategies: Codesign vs. low-C protection.
Microelectron. Reliab., 2007

A 90-nm CMOS Low-Power GSM/EDGE Multimedia-Enhanced Baseband Processor With 380-MHz ARM926 Core and Mixed-Signal Extensions.
IEEE J. Solid State Circuits, 2007

A Complementary Switched MOSFET Architecture for the 1/f Noise Reduction in Linear Analog CMOS ICs.
IEEE J. Solid State Circuits, 2007

In-Situ Delay Characterization and Local Supply Voltage Adjustment for Compensation of Local Parametric Variations.
IEEE J. Solid State Circuits, 2007

A 10GHz Broadband Amplifier with Bootstrapped 2kV ESD Protection.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

An Integrated Gravimetric FBAR Circuit for Operation in Liquids Using a Flip-Chip Extended 0.13μm CMOS Technology.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Transient Variations in Emerging SOI Technologies: Modeling and Impact on Analog/Mixed-Signal Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Advances in Multi-Gate MOSFET Circuit Design.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

A configurable High-Side/ low-Side Driver.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Variation tolerant high resolution and low latency time-to-digital converter.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Analog design challenges and trade-offs using emerging materials and devices.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Layout options for stability tuning of SRAM cells in multi-gate-FET technologies.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006
Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead.
IEEE J. Solid State Circuits, 2006

Pattern Pruner: Automatic Pattern Size Reduction Method that Uses Computational Intelligence-Based Testing.
Proceedings of the 2006 IEEE International Test Conference, 2006

A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 24x16 CMOS-Based Chronocoulometric DNA Microarray.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
High abstraction level permutational ESD concept analysis.
Microelectron. Reliab., 2005

Power-Clock Gating in Adiabatic Logic Circuits.
Proceedings of the Integrated Circuit and System Design, 2005

Computational intelligence based testing for semiconductor measurement systems.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

CMOS sensor array for electrical imaging of neuronal activity.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Energieoptimierung durch Adiabatische Schaltungstechnik.
Proceedings of the 35. Jahrestagung der Gesellschaft für Informatik, 2005

Impact of process parameter variations on the energy dissipation in adiabatic logic.
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Computational Intelligence Characterization Method of Semiconductor Device.
Proceedings of the 2005 Design, 2005

Making adiabatic circuits attractive for todays VLSI industry by multi-mode operation-adiabatic mode circuits.
Proceedings of the Second Conference on Computing Frontiers, 2005

Scaling trends in adiabatic logic.
Proceedings of the Second Conference on Computing Frontiers, 2005

2004
Design of low-voltage MOSFET-only ΣΔ modulators in standard digital CMOS technology.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Analysis of PowerMOSFET chips failed in thermal instability.
Microelectron. Reliab., 2004

Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits.
Proceedings of the Integrated Circuit and System Design, 2004

Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption.
Proceedings of the Integrated Circuit and System Design, 2004

Power Supply Net for Adiabatic Circuits.
Proceedings of the Integrated Circuit and System Design, 2004

The tunnelling field effect transistors (TFET): the temperature dependence, the simulation model, and its application.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
Hot-Spot Meaurements and Analysis of Electro-Thermal Effects in Low-Voltage Power-MOSFET's.
Microelectron. Reliab., 2003

Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Evolution of automatic semiconductor test equipment: automatic test pattern learning, classification, optimisation and generation for power supply noise.
Proceedings of the IEEE International Conference on Virtual Environments, 2003

Reduction of the Energy Consumption in Adiabatic Gates by Optimal Transistor Sizing.
Proceedings of the Integrated Circuit and System Design, 2003

0.65V sigma-delta modulators.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Design of an integrated potentiostat circuit for CMOS bio sensor chips.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits.
Proceedings of the 8th European Test Workshop, 2003

2002
Reliability analysis of power MOSFET's with the help of compact models and circuit simulation.
Microelectron. Reliab., 2002

2001
A low-voltage MOSFET-only Sigma-Delta modulator for speech band applications using depletion-mode MOS-capacitors in combined series and parallel compensation.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1997
The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1997

1995
A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1990
Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990


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