Suhas Shivapakash

Orcid: 0000-0002-9173-213X

According to our database¹, Suhas Shivapakash authored at least 3 papers between 2020 and 2021.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2021

FantastIC4: A Hardware-Software Co-Design Approach for Efficiently Running 4Bit-Compact Multilayer Perceptrons.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2021

A Power Efficiency Enhancements of a Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks.

[BibT_eX]

[DOI]

IEEE Open J. Circuits Syst., 2021

2020

A Power Efficient Multi-Bit Accelerator for Memory Prohibitive Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Suhas Shivapakash

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...