Süleyman Sirri Demirsoy

According to our database1, Süleyman Sirri Demirsoy authored at least 18 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
DASH: Asynchronous Hardware Data Processing Services.
Proceedings of the 13th Conference on Innovative Data Systems Research, 2023

2022
Bandwidth-optimal Relational Joins on FPGAs.
Proceedings of the 25th International Conference on Extending Database Technology, 2022

2020
Faster & strong: string dictionary compression using sampling and fast vectorized decompression.
VLDB J., 2020

Accelerating re-pair compression using FPGAs.
Proceedings of the 16th International Workshop on Data Management on New Hardware, 2020

2019
Fast & Strong: The Case of Compressed String Dictionaries on Modern CPUs.
Proceedings of the 15th International Workshop on Data Management on New Hardware, 2019

2009
SoC framework for FPGA: A case study of LTE PUSCH receiver.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Cholesky decomposition using fused datapath synthesis.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

2008
Session MA5: Programmable and reconfigurable architectures.
Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

2006
A computationally efficient DAB bit-stream processor.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Low-Complexity Self-Calibrating Adaptive Quadrature Receiver.
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005
Synthesis of reconfigurable multiplier blocks: part - II algorithm.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Synthesis of reconfigurable multiplier blocks: part I - fundamentals.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Efficient FPGA implementation of an adaptive IQ-imbalance corrector for communication receivers using reduced range multipliers.
Proceedings of the 13th European Signal Processing Conference, 2005

2003
Design guidelines for reconfigurable multiplier blocks.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Reconfigurable implementation of recursive DCT kernels for reduced quantization noise.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Designing multiplier blocks with low logic depth.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Power analysis of multiplier blocks.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2000
Transition analysis on FPGA for multiplier-block based FIR filter structures.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000


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