Sunrui Zhang

Orcid: 0009-0000-9539-1427

According to our database1, Sunrui Zhang authored at least 11 papers between 2022 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
MarchGen: A March Sequence Generation Method for Faults With an Arbitrary Number of Operations in RAMs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2026

A Reconfigurable Built-In Self-Test Scheme for the Evaluation Circuits of Digital SRAM-IMC Architectures.
IEEE Trans. Very Large Scale Integr. Syst., January, 2026

2025
A VC Dimension-Oriented Improvement Method of PUFs for the Anti-Modeling-Attack Capability.
ACM Trans. Embed. Comput. Syst., September, 2025

In-Memory Logic Synthesis Methods based on Read Decoupled 8T and Transpose 11T SRAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

2024
An in-Array Build-In Self-Test Scheme for Embedded SRAM Array.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2024

An 11T SRAM Cell for the Dual-Direction In-Array Logic/CAM Operations.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Design of a UE5-based digital twin platform.
CoRR, 2024

A Convolutional Spiking Neural Network Accelerator with the Sparsity-Aware Memory and Compressed Weights.
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023
An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array.
IEEE Trans. Computers, December, 2023

2022
An Area-Efficient and Robust Memristive LUT Based on the Enhanced Scouting Logic Cells.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic Gates.
Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022


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