Xiaoxin Cui

According to our database, Xiaoxin Cui authored at least 88 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support.

Qingyu Guo, Nanbing Pan, Xin Qiao, Xiaoxin Cui, Yuan Wang

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Dy-MFNS-CAC: An Encoding Mechanism to Suppress the Crosstalk and Repair the Hard Faults in Rectangular TSV Arrays.

Chen Wei, Xiaole Cui, Xiaoxin Cui

IEEE Trans. Reliab., March, 2024

The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice.

Yongliang Chen, Xiaole Cui, Xiaoxin Cui, Xing Zhang

Microelectron. J., February, 2024

The Resistance Analysis Attack and Security Enhancement of the IMC LUT Based on the Complementary Resistive Switch Cells.

Xiaole Cui, Mingqi Yin, Hanqing Liu, Xiaoxin Cui

ACM Trans. Design Autom. Electr. Syst., January, 2024

2023

An Area-Efficient In-Memory Implementation Method of Arbitrary Boolean Function Based on SRAM Array.

Sunrui Zhang, Xiaole Cui, Feng Wei, Xiaoxin Cui

IEEE Trans. Computers, December, 2023

Toward a Lossless Conversion for Spiking Neural Networks with Negative-Spike Dynamics.

Chenglong Zou, Xiaoxin Cui, Guang Chen, Yuanyuan Jiang, Yuan Wang

Adv. Intell. Syst., December, 2023

An Efficient Neuromorphic Implementation of Temporal Coding-Based On-Chip STDP Learning.

Yi Zhong, Zilin Wang, Xiaoxin Cui, Jian Cao, Yuan Wang

IEEE Trans. Circuits Syst. II Express Briefs, November, 2023

LRTransDet: A Real-Time SAR Ship-Detection Network with Lightweight ViT and Multi-Scale Feature Fusion.

Kunyu Feng, Li Lun, Xiaofeng Wang, Xiaoxin Cui

Remote. Sens., November, 2023

A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation.

Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Jiahao Song, Haoyang Luo, Xin'an Wang, Yuan Wang

IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array.

Xiaole Cui, Chen Wei, Xu Feng, Xiaoxin Cui

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

Real-Time Target Tracking System With Spiking Neural Networks Implemented on Neuromorphic Chips.

Kefei Liu, Xiaoxin Cui, Xiang Ji, Yisong Kuang, Chenglong Zou, Yi Zhong, Kanglin Xiao, Yuan Wang

IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

An Evaluation Method of the Anti-Modeling-Attack Capability of PUFs.

Yongliang Chen, Xiaole Cui, Yun Liu, Xiaoxin Cui

IEEE Trans. Inf. Forensics Secur., 2023

A Spiking Neural Network Accelerator based on Ping-Pong Architecture with Sparse Spike and Weight.

Zilin Wang, Yi Zhong, Xiaoxin Cui, Yisong Kuang, Yuan Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

An Efficient Spiking Neural Network Accelerator with Sparse Weight.

Zilin Wang, Yi Zhong, Youming Yang, Xiaoxin Cui, Yuan Wang

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

Unsupervised Learning of Spike-Timing-Dependent Plasticity Based on a Neuromorphic Implementation.

Yi Zhong, Zilin Wang, Xiaoxin Cui, Jian Cao, Yuan Wang

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator.

Yisong Kuang, Xiaoxin Cui, Zilin Wang, Chenglong Zou, Yi Zhong, Kefei Liu, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang

IEEE Trans. Very Large Scale Integr. Syst., 2022

A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling.

Xin Qiao, Jiahao Song, Xiyuan Tang, Haoyang Luo, Nanbing Pan, Xiaoxin Cui, Runsheng Wang, Yuan Wang

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Modular building blocks for mapping spiking neural networks onto a programmable neuromorphic processor.

Chenglong Zou, Xiaoxin Cui, Guang Chen, Shuo Feng, Kefei Liu, Xinan Wang, Yuan Wang

Microelectron. J., 2022

A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications.

Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang

Microelectron. J., 2022

A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec.

Chen Wei, Xiaole Cui, Xiaoxin Cui

IEEE Des. Test, 2022

Towards Lossless ANN-SNN Conversion under Ultra-Low Latency with Dual-Phase Optimization.

Ziming Wang, Shuang Lian, Yuhao Zhang, Xiaoxin Cui, Rui Yan, Huajin Tang

CoRR, 2022

A Comparative Study on the Performance and Security Evaluation of Spiking Neural Networks.

Yanjie Li, Xiaoxin Cui, Yihao Zhou, Ying Li

IEEE Access, 2022

A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation.

Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Nanbing Pan, Xin'an Wang, Yuan Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro.

Nanbing Pan, Xiaoxin Cui, Xin Qiao, Kanglin Xiao, Qingyu Guo, Yuan Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight.

Yisong Kuang, Xiaoxin Cui, Chenglong Zou, Yi Zhong, Zhenhui Dai, Zilin Wang, Kefei Liu, Dunshan Yu, Yuan Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 4-bit Integer-Only Neural Network Quantization Method Based on Shift Batch Normalization.

Qingyu Guo, Xiaoxin Cui, Jian Zhang, Aifei Zhang, Xinjie Guo, Yuan Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

An Area-Efficient and Robust Memristive LUT Based on the Enhanced Scouting Logic Cells.

Xiaole Cui, Fan Liu, Sunrui Zhang, Xiaoxin Cui

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations.

Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Xin'an Wang, Yuan Wang

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

An obfuscation scheme of scan chain to protect the cryptographic chips.

Huixian Huang, Xiaole Cui, Shuming Zhang, Ge Li, Xiaoxin Cui

Proceedings of the IEEE 31st Asian Test Symposium, 2022

A Hybrid Spiking Recurrent Neural Network on Hardware for Efficient Emotion Recognition.

Chenglong Zou, Xiaoxin Cui, Yisong Kuang, Yuan Wang, Xinan Wang

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

A Full-Neuron Memory Model Designed for Neuromorphic Systems.

Kefei Liu, Xiaoxin Cui, Chenglong Zou, Yisong Kuang, Yi Zhong, Kanglin Xiao, Yuan Wang

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

A Mapping Model of SNNs to Neuromorphic Hardware.

Xiuping Cui, Xiaochen Hao, Yun Liang, Guangyu Sun, Xiaoxin Cui, Yuan Wang, Ru Huang

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS.

Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Yuan Wang, Dunshan Yu, Ru Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Machine Learning Aided Key-Guessing Attack Paradigm Against Logic Block Encryption.

Yi Zhong, Jianhua Feng, Xiaoxin Cui, Xiaole Cui

J. Comput. Sci. Technol., 2021

28nm asynchronous area-saving AES processor with high Common and Machine learning side-channel attack resistance.

Qingyun Zou, Xiaoxin Cui, Zhenhui Dai, Yisong Kuang, Yi Zhong, Chenglong Zou, Xiaole Cui

IEICE Electron. Express, 2021

Integer-Only Neural Network Quantization Scheme Based on Shift-Batch-Normalization.

Qingyu Guo, Yuan Wang, Xiaoxin Cui

CoRR, 2021

The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates.

Xiaole Cui, Ye Ma, Feng Wei, Xiaoxin Cui

IEEE Access, 2021

The Security Enhancement Techniques of the Double-layer PUF Against the ANN-based Modeling Attack.

Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui

Proceedings of the IEEE International Test Conference, 2021

The ANN Based Modeling Attack and Security Enhancement of the Double-layer PUF.

Xiaole Cui, Yongliang Chen, Wenqiang Ye, Xiaoxin Cui

Proceedings of the IEEE International Test Conference in Asia, 2021

A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS.

Yi Zhong, Xiaoxin Cui, Yisong Kuang, Kefei Liu, Yuan Wang, Ru Huang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations.

Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

An SNN-Based and Neuromorphic-Hardware-Implementable Noise Filter with Self-adaptive Time Window for Event-Based Vision Sensor.

Kanglin Xiao, Xiaoxin Cui, Kefei Liu, Xiaole Cui, Xin'an Wang

Proceedings of the International Joint Conference on Neural Networks, 2021

The Modeling Attack and Security Enhancement of the XbarPUF with Both Column Swapping and XORing.

Yongliang Chen, Xiaole Cui, Wenqiang Ye, Xiaoxin Cui

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

A fully asynchronous QDI mesh router based on 28nm standard cells.

Qingyun Zou, Xiaoxin Cui, Yi Zhong, Zhenhui Dai, Yisong Kuang

Proceedings of the 14th IEEE International Conference on ASIC, 2021

The logic obfuscation of LFSR with the crosstalk based polymorphic gate.

Yuqian Sun, Xiaole Cui, Yongliang Chen, Xiaoxin Cui

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

A Novel Circuit Authentication Scheme Based on Partial Polymorphic Gates.

Timothy Dunlap, Omid Aramoon, Gang Qu, Tian Wang, Xiaoxin Cui, Dunshan Yu

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

2020

The synthesis method of logic circuits based on the iMemComp gates.

Xiaole Cui, Qiujun Lin, Xiaoxin Cui, Feng Wei, Xiaoyan Liu, Jinfeng Kang

Integr., 2020

Design of High-Speed Logic Circuits with Four-Step RRAM-Based Logic Gates.

Xiaole Cui, Xiao Ma, Qiujun Lin, Xiang Li, Hang Zhou, Xiaoxin Cui

Circuits Syst. Signal Process., 2020

A synthesis method for logic circuits in RRAM arrays.

Xiaole Cui, Xiao Ma, Feng Wei, Xiaoxin Cui

Sci. China Inf. Sci., 2020

A Novel Conversion Method for Spiking Neural Network using Median Quantization.

Chenglong Zou, Xiaoxin Cui, Jiexian Ge, Hanghang Ma, Xin'an Wang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Testability Enhancement Method for the Memristor Ratioed Logic Circuits.

Li Qu, Xiaole Cui, Xiaoxin Cui

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

A Sparse Event-Driven Unsupervised Learning Network with Adaptive Exponential Integrate-and-Fire Model.

Zhao Zhao, Yuan Wang, Cheng Li, Xiaoxin Cui, Ru Huang

Proceedings of the International Conference on IC Design and Technology, 2019

An Energy-Efficient Computing-in-Memory Neuromorphic System with On-Chip Training.

Zhao Zhao, Yuan Wang, Xinyue Zhang, Xiaoxin Cui, Ru Huang

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

Deep Spiking Convolutional Neural Networks for Programmable Neuro-synaptic System.

Chenglong Zou, Xin'an Wang, Boxing Xu, Yisong Kuang, Xiaoxin Cui

Proceedings of the 13th IEEE International Conference on ASIC, 2019

BNReLU: Combine Batch Normalization and Rectified Linear Unit to Reduce Hardware Overhead.

Jiexian Ge, Xiaoxin Cui, Kanglin Xiao, Chenglong Zou, Yi-Hsiang Chen, Rongshan Wei

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Improved Discrete Wavelet Analysis and Principal Component Analysis for EEG Signal Processing.

Yi-Hsiang Chen, Xiaoxin Cui, Kanglin Xiao, Dunshan Yu

Proceedings of the 13th IEEE International Conference on ASIC, 2019

2018

Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits.

Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui

IEEE Trans. Very Large Scale Integr. Syst., 2018

Design of Low-Power High-Performance FinFET Standard Cells.

Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Dunshan Yu, Xiaole Cui

Circuits Syst. Signal Process., 2018

A Novel Polymorphic Gate Based Circuit Fingerprinting Technique.

Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition.

Cheng Li, Yuan Wang, Jin Zhang, Xiaoxin Cui, Ru Huang

Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

Polymorphic gate based IC watermarking techniques.

Tian Wang, Xiaoxin Cui, Dunshan Yu, Omid Aramoon, Timothy Dunlap, Gang Qu, Xiaole Cui

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias.

Xiaole Cui, Xiaoxin Cui, Yewen Ni, Min Miao, Yufeng Jin

IEEE Trans. Very Large Scale Integr. Syst., 2017

High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ).

Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui

IEEE Trans. Ind. Electron., 2017

Improving DFA attacks on AES with unknown and random faults.

Nan Liao, Xiaoxin Cui, Kai Liao, Tian Wang, Dunshan Yu, Xiaole Cui

Sci. China Inf. Sci., 2017

Testing of 1T<i>n</i>R RRAM array with sneak path technique.

Xiaole Cui, Qiang Zhang, Xiaoxin Cui, Xin'an Wang, Jinfeng Kang, Xiaoyan Liu

Sci. China Inf. Sci., 2017

A Heuristic Algorithm for Automatic Generation of March Tests.

Xiaole Cui, Yichi Luo, Qiujun Lin, Xiaoxin Cui

Proceedings of the 26th IEEE Asian Test Symposium, 2017

A signal noise separation method for the instant mixing linear and nonlinear circuits with MISEP algorithm.

Liwen Zhu, Xiaole Cui, Xiang Li, Xiaoxin Cui

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A design of high performance full adder with memristors.

Kuimin Zhang, Xiaole Cui, Xiaoxin Cui

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Improving DFA on AES using all-fault ciphertexts.

Yewen Ni, Xiaoxin Cui, Tian Wang, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Design of router for spiking neural networks.

Yewen Ni, Xiaoxin Cui, Yuanning Fan, Qiankun Han, Kefei Liu, Xiaole Cui

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A hybrid fault model for differential fault attack on AES.

Yixia Liu, Xiaoxin Cui, Jian Cao, Xing Zhang

Proceedings of the 12th IEEE International Conference on ASIC, 2017

A practical cold boot attack on RSA private keys.

Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui, Gang Qu

Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016

Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology.

Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Xiaole Cui, Dunshan Yu

IEICE Trans. Electron., 2016

Ultralow-power high-speed flip-flop based on multimode FinFETs.

Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Dunshan Yu, Xiaole Cui

Sci. China Inf. Sci., 2016

2015

Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure.

Zuolin Cheng, Xiaole Cui, Xiaoxin Cui, Chung Len Lee

IET Comput. Digit. Tech., 2015

Key characterization factors of accurate power modeling for FinFET circuits.

Kaisheng Ma, Xiaoxin Cui, Kai Liao, Nan Liao, Di Wu, Dunshan Yu

Sci. China Inf. Sci., 2015

Employing the mixed FBB/RBB in the design of FinFET logic gates.

Tian Wang, Xiaoxin Cui, Kai Liao, Nan Liao, Yewen Ni, Dunshan Yu, Xiaole Cui

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A countermeasure for power analysis to scalar multiplication of ECC hardware.

Lifei Liu, Xiaole Cui, Yalin Ran, Xiaoxin Cui

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications.

Nan Liao, Xiaoxin Cui, Tian Wang, Kai Liao, Yewen Ni, Dunshan Yu, Xiaole Cui

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014

Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs.

Kai Liao, Xiaoxin Cui, Nan Liao, Kaisheng Ma, Di Wu, Wei Wei, Rui Li, Dunshan Yu

Sci. China Inf. Sci., 2014

Low power adiabatic logic based on FinFETs.

Nan Liao, Xiaoxin Cui, Kai Liao, Kaisheng Ma, Di Wu, Wei Wei, Rui Li, Dunshan Yu

Sci. China Inf. Sci., 2014

High-speed constant-time division module for Elliptic Curve Cryptography based on GF(2^m).

Kai Liao, Xiaoxin Cui, Nan Liao, Tian Wang, Xiao Zhang, Ying Huang, Dunshan Yu

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013

Leakage Power Reduction of Adiabatic Circuits Based on FinFET Devices.

Kai Liao, Xiaoxin Cui, Nan Liao, Kaisheng Ma

IEICE Trans. Electron., 2013

A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs.

Xiaoxin Cui, Kaisheng Ma, Kai Liao, Nan Liao, Di Wu, Wei Wei, Rui Li, Dunshan Yu

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

New DfT architectures for 3D-SICs with a wireless test port.

Yibo He, Xiaole Cui, Chung Len Lee, Xiaoxin Cui, Yufeng Jin

Proceedings of the IEEE 10th International Conference on ASIC, 2013

AHardware implementation of DES with combined countermeasure against DPA.

Xiaoxin Cui, Rui Li, Wei Wei, Juan Gu, Xiaole Cui

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2011

A JTAG-based configuration circuit applied in SerDes chip.

Xun Jiang, Xiaoxin Cui, Dunshan Yu

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2006

Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm.

Xiaoxin Cui, Dunshan Yu, Shimin Sheng, Xiaole Cui

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006