Xiaoxin Cui

According to our database1, Xiaoxin Cui authored at least 32 papers between 2006 and 2018.

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Bibliography

2018
Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits.
IEEE Trans. VLSI Syst., 2018

Design of Low-Power High-Performance FinFET Standard Cells.
CSSP, 2018

A Novel Polymorphic Gate Based Circuit Fingerprinting Technique.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

Polymorphic gate based IC watermarking techniques.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias.
IEEE Trans. VLSI Syst., 2017

High-Performance Noninvasive Side-Channel Attack Resistant ECC Coprocessor for GF(2m ).
IEEE Trans. Industrial Electronics, 2017

Improving DFA attacks on AES with unknown and random faults.
SCIENCE CHINA Information Sciences, 2017

Testing of 1TnR RRAM array with sneak path technique.
SCIENCE CHINA Information Sciences, 2017

A Heuristic Algorithm for Automatic Generation of March Tests.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

A signal noise separation method for the instant mixing linear and nonlinear circuits with MISEP algorithm.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A design of high performance full adder with memristors.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Improving DFA on AES using all-fault ciphertexts.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

Design of router for spiking neural networks.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A hybrid fault model for differential fault attack on AES.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

A practical cold boot attack on RSA private keys.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
Low Power High Performance FinFET Standard Cells Based on Mixed Back Biasing Technology.
IEICE Transactions, 2016

Ultralow-power high-speed flip-flop based on multimode FinFETs.
SCIENCE CHINA Information Sciences, 2016

2015
Self-heating burn-in pattern generation based on the genetic algorithm incorporated with a BACK-like procedure.
IET Computers & Digital Techniques, 2015

Key characterization factors of accurate power modeling for FinFET circuits.
SCIENCE CHINA Information Sciences, 2015

Employing the mixed FBB/RBB in the design of FinFET logic gates.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A countermeasure for power analysis to scalar multiplication of ECC hardware.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Ultra-low power dissipation of improved complementary pass-transistor adiabatic logic circuits based on FinFETs.
SCIENCE CHINA Information Sciences, 2014

Low power adiabatic logic based on FinFETs.
SCIENCE CHINA Information Sciences, 2014

High-speed constant-time division module for Elliptic Curve Cryptography based on GF(2m).
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Leakage Power Reduction of Adiabatic Circuits Based on FinFET Devices.
IEICE Transactions, 2013

A Dynamic-Adjusting Threshold-Voltage Scheme for FinFETs low power designs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

New DfT architectures for 3D-SICs with a wireless test port.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

AHardware implementation of DES with combined countermeasure against DPA.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2011
A JTAG-based configuration circuit applied in SerDes chip.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2006
Design and Implementation of a 2-level FSK Digital Modems Using CORDIC Algorithm.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006


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