Sushanta Bordoloi

According to our database, Sushanta Bordoloi authored at least 3 papers between 2017 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

Introspection Into Reliability Aspects in AlGaN/GaN HEMTs With Gate Geometry Modification.

Sushanta Bordoloi, Ashok Ray, Gaurav Trivedi

IEEE Access, 2021

2019

Current Collapse Reduction Technique Using N-Doped Buffer Layer into the Bulk Region of a Gate Injection Transistor.

Koushik Bharadwaj, Ashok Ray, Sushanta Bordoloi, Gaurav Trivedi

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

2017

FEM Based Device Simulator for High Voltage Devices.

Ashok Ray, Gaurav Kumar, Sushanta Bordoloi, Dheeraj Kumar Sinha, Pratima Agarwal, Gaurav Trivedi

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017