Sutirtha Bhattacharyya

Orcid: 0009-0002-4786-8627

According to our database1, Sutirtha Bhattacharyya authored at least 5 papers between 2024 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
LInC-BMC: A Lookahead Informed Clause Deletion Mechanism for Bounded Model Checking.
Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

2025
LHS: LLM Assisted Efficient High-level Synthesis of Deep Learning Tasks.
ACM Trans. Design Autom. Electr. Syst., November, 2025

LAMA: A Latency Minimum Resource Constraint Accelerator for CNN Models.
Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

New Branching Heuristics for Incremental Bounded Model Checking.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

2024
LLM vs HLS for RTL Code Generation: Friend or Foe?
Proceedings of the 33rd IEEE Asian Test Symposium, 2024


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