Chandan Karfa

According to our database1, Chandan Karfa authored at least 30 papers between 2006 and 2020.

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Bibliography

2020
Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Verification of Scheduling of Conditional Behaviors in High-Level Synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.
CoRR, 2020

Automatic Inverse Operation Detection and its Impact in High-level Synthesis.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Is Register Transfer Level Locking Secure?
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Translation Validation of Code Motion Transformations Involving Loops.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Counter-example generation procedure for path-based equivalence checkers.
IET Softw., 2019

Verification of parallelising transformations of KPN models.
IET Cyper-Phys. Syst.: Theory & Appl., 2019

A Quick Introduction to Functional Verification of Array-Intensive Programs.
CoRR, 2019

Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

User Guided Register Manipulation in Digital Circuits.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Formal Verification of Optimizing Transformations during High-level Synthesis.
Proceedings of the 12th Innovations on Software Engineering Conference (formerly known as India Software Engineering Conference), 2019

2018
Compiler-agnostic Translation Validation.
Proceedings of the 11th Innovations in Software Engineering Conference, ISEC 2018, Hyderabad, India, February 09, 2018

Automatic detection of inverse operations while avoiding loop unrolling.
Proceedings of the 40th International Conference on Software Engineering: Companion Proceeedings, 2018

2017
xMAS Based Accurate Modeling and Progress Verification of NoCs.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Translation Validation of Loop Invariant Code Optimizations Involving False Computations.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2014
Verification of Code Motion Techniques Using Value Propagation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013
Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Verification of KPN Level Transformations.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012
Formal verification of code motion techniques using data-flow-driven equivalence checking.
ACM Trans. Design Autom. Electr. Syst., 2012

A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques.
Proceedings of the International Symposium on Electronic System Design, 2012

2011
Verification of Register Transfer Level Low Power Transformations.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Equivalence Checking of Array-Intensive Programs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010
Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2008
An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007
Register Sharing Verification During Data-Path Synthesis.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Hand-in-hand verification of high-level synthesis.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
Verification of Scheduling in High-level Synthesis.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

A Formal Verification Method of Scheduling in High-level Synthesis.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006


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