Chandan Karfa

According to our database, Chandan Karfa authored at least 56 papers between 2006 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation.

Bhabesh Mali, Karthik Maddala, Sweeya Reddy, Vatsal Gupta, Chandan Karfa, Ramesh Karri

CoRR, 2024

ERS: Energy-efficient Real-time DAG Scheduling on Uniform Multiprocessor Embedded Systems.

Debabrata Senapati, Dharmendra Maurya, Arnab Sarkar, Chandan Karfa

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

SRIL: Securing Registers from Information Leakage at Register Transfer Level.

Priyanka Panigrahi, Vignesh Ravichandra Rao, Thockchom Birjit Singha, Chandan Karfa

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Evaluating the Robustness of Large scale eFPGA-based Hardware Redaction.

Praveen Karmakar, Marpina Bharani, Chandan Karfa

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems.

Debabrata Senapati, Kousik Rajesh, Chandan Karfa, Arnab Sarkar

ACM Trans. Design Autom. Electr. Syst., November, 2023

Translation Validation of Information Leakage of Compiler Optimizations.

Priyanka Panigrahi, Chandan Karfa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Energy-Aware Real-Time Scheduling of Multiple Periodic DAGs on Heterogeneous Systems.

Debabrata Senapati, Arnab Sarkar, Chandan Karfa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

An Investigation into the Security of Register Allocation with Spilling and Splitting.

Priyanka Panigrahi, Chandan Karfa

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

2022

Quantifying Information Leakage for Security Verification of Compiler Optimizations.

Priyanka Panigrahi, Abhik Paul, Chandan Karfa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

FastSim: A Fast Simulation Framework for High-Level Synthesis.

Mohammed Abderehman, Jayprakash Patidar, Jay H. Oza, Yom Nigam, T. M. Abdul Khader, Chandan Karfa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

BLAST: Belling the Black-Hat High-Level Synthesis Tool.

Mohammed Abderehman, Rupak Gupta, Theegala Rakesh Reddy, Chandan Karfa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

PRESTO: A Penalty-Aware Real-Time Scheduler for Task Graphs on Heterogeneous Platforms.

Debabrata Senapati, Arnab Sarkar, Chandan Karfa

IEEE Trans. Computers, 2022

Secure Register Allocation for Trusted Code Generation.

Priyanka Panigrahi, Vemuri Sahithya, Chandan Karfa, Prabhat Mishra

IEEE Embed. Syst. Lett., 2022

Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC.

Surajit Das, Chandan Karfa

IEEE Embed. Syst. Lett., 2022

Accelerating NoC Verification Using a Complete Model and Active Window.

Surajit Das, Chandan Karfa, Santosh Biswas

IEEE Access, 2022

Corruption Exposes You: Statistical Key Recovery from Compound Logic Locking.

Arshdeep Kaur, Sayandeep Saha, Chandan Karfa, Debdeep Mukhopadhyay

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

DEEQ: Data-driven End-to-End EQuivalence Checking of High-level Synthesis.

Mohammed Abderehman, Theegala Rakesh Reddy, Chandan Karfa

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Performance-Effective DAG Scheduling for Heterogeneous Distributed Systems.

Debabrata Senapati, Arnab Sarkar, Chandan Karfa

Proceedings of the ICDCN '22: 23rd International Conference on Distributed Computing and Networking, Delhi, AA, India, January 4, 2022

GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking.

Gagan Gayari, Chandan Karfa, Prithwijit Guha

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

ImageSpec: Efficient High-Level Synthesis of Image Processing Applications.

Abdul Khader Thalakkattu Moosa, Nilotpola Sarma, Chandan Karfa

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021

HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems.

Debabrata Senapati, Arnab Sarkar, Chandan Karfa

ACM Trans. Embed. Comput. Syst., 2021

VP_TT: A value propagation based equivalence checker for testability transformations.

Ramanuj Chouksey, Sachin Kumar Maddheshiya, Chandan Karfa

IET Softw., 2021

Reverse Engineering Register to Variable Mapping in High-level Synthesis.

Mohammed Abderehman, Rupak Gupta, Chandan Karfa

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

HOST: HLS Obfuscations against SMT ATtack.

Chandan Karfa, T. M. Abdul Khader, Yom Nigam, Ramanuj Chouksey, Ramesh Karri

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock.

Surajit Das, Chandan Karfa, Santosh Biswas

IEEE Trans. Very Large Scale Integr. Syst., 2020

Verification of Scheduling of Conditional Behaviors in High-Level Synthesis.

Ramanuj Chouksey, Chandan Karfa

IEEE Trans. Very Large Scale Integr. Syst., 2020

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.

Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md. Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks

CoRR, 2020

Automatic Inverse Operation Detection and its Impact in High-level Synthesis.

Pankaj Kumar Kalita, Ramanuj Chouksey, Chandan Karfa

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Is Register Transfer Level Locking Secure?

Chandan Karfa, Ramanuj Chouksey, Christian Pilato, Siddharth Garg, Ramesh Karri

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

SAT Based Partial Attack on Compound Logic Locking.

Melbin John, Aadil Hoda, Ramanuj Chouksey, Chandan Karfa

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020

2019

Translation Validation of Code Motion Transformations Involving Loops.

Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Counter-example generation procedure for path-based equivalence checkers.

Ramanuj Chouksey, Chandan Karfa, Kunal Banerjee, Pankaj Kumar Kalita, Purandar Bhaduri

IET Softw., 2019

Verification of parallelising transformations of KPN models.

Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal

IET Cyper-Phys. Syst.: Theory & Appl., 2019

A Quick Introduction to Functional Verification of Array-Intensive Programs.

Kunal Banerjee, Chandan Karfa

CoRR, 2019

Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples.

Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

User Guided Register Manipulation in Digital Circuits.

Priyanka Panigrahi, Rajesh Kumar Jha, Chandan Karfa

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Formal Verification of Optimizing Transformations during High-level Synthesis.

Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri

Proceedings of the 12th Innovations on Software Engineering Conference (formerly known as India Software Engineering Conference), 2019

2018

Compiler-agnostic Translation Validation.

Kunal Banerjee, Chandan Karfa

Proceedings of the 11th Innovations in Software Engineering Conference, ISEC 2018, Hyderabad, India, February 09, 2018

Automatic detection of inverse operations while avoiding loop unrolling.

Kunal Banerjee, Ramanuj Chouksey, Chandan Karfa, Pankaj Kumar Kalita

Proceedings of the 40th International Conference on Software Engineering: Companion Proceeedings, 2018

2017

xMAS Based Accurate Modeling and Progress Verification of NoCs.

Surajit Das, Chandan Karfa, Santosh Biswas

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Translation Validation of Loop Invariant Code Optimizations Involving False Computations.

Ramanuj Chouksey, Chandan Karfa, Purandar Bhaduri

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2014

Verification of Code Motion Techniques Using Value Propagation.

Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013

Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors.

Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Verification of KPN Level Transformations.

Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012

Formal verification of code motion techniques using data-flow-driven equivalence checking.

Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar

ACM Trans. Design Autom. Electr. Syst., 2012

A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques.

Kunal Banerjee, Chandan Karfa, Dipankar Sarkar, Chittaranjan Mandal

Proceedings of the International Symposium on Electronic System Design, 2012

2011

Verification of Register Transfer Level Low Power Transformations.

Chandan Karfa, Chitta Mandal, Dipankar Sarkar

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Equivalence Checking of Array-Intensive Programs.

Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chitta Mandal

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010

Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits.

Chandan Karfa, Dipankar Sarkar, Chitta Mandal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques.

Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2008

An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.

Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007

Register Sharing Verification During Data-Path Synthesis.

Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, Chris Reade

Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Hand-in-hand verification of high-level synthesis.

Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal, Chris Reade

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

Verification of Scheduling in High-level Synthesis.

Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

A Formal Verification Method of Scheduling in High-level Synthesis.

Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sarkar, S. R. Pentakota, Chris Reade

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Fairness of transitions in diagnosability analysis of hybrid systems.

Santosh Biswas, Chandan Karfa, Himani Kanwar, Dipankar Sarkar, Siddhartha Mukhopadhyay, Amit Patra

Proceedings of the American Control Conference, 2006