Raj Kumar Gajavelly

According to our database, Raj Kumar Gajavelly authored at least 14 papers between 2014 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

LInC-BMC: A Lookahead Informed Clause Deletion Mechanism for Bounded Model Checking.

Satyam Shubham, Sutirtha Bhattacharyya, Ansuman Banerjee, Raj Kumar Gajavelly

Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

MPBMC: Multi-Property Bounded Model Checking with GNN-Guided Clustering.

Soumik Guha Roy, Sumana Ghosh, Ansuman Banerjee, Raj Kumar Gajavelly, Sudhakar Surendran

Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

SuperSAGA: A Supervisor-Subordinate Agentic workflow for the Generation of Assertions.

Subhajit Paul, Ansuman Banerjee, Sumana Ghosh, Sudhakar Surendran, Raj Kumar Gajavelly

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

BMC Engine Sequencing with Graph Neural Network Embeddings of Hardware Circuits.

Soumik Guha Roy, Adriz Chanda, Prateek Ganguli, Sumana Ghosh, Ansuman Banerjee, Raj Kumar Gajavelly, Sudhakar Surendran

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

New Branching Heuristics for Incremental Bounded Model Checking.

Satyam Shubham, Sutirtha Bhattacharyya, Ansuman Banerjee, Raj Kumar Gajavelly

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

LISA: LLM Informed Systemverilog Assertion generation with RAG and Chain-of-Thought.

Subhajit Paul, Ansuman Banerjee, Sumana Ghosh, Sudhakar Surendran, Raj Kumar Gajavelly

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2025

2024

MAB-BMC: A Formal Verification Enhancer by Harnessing Multiple BMC Engines Together.

Devleena Ghosh, Sumana Ghosh, Ansuman Banerjee, Raj Kumar Gajavelly, Sudhakar Surendran

ACM Trans. Design Autom. Electr. Syst., 2024

Toward Exhaustive Sequential Redundancy Removal.

Rohit Dureja, Jason Baumgartner, Raj Kumar Gajavelly, Robert Kanzelman, Kristin Y. Rozier

Proceedings of the Formal Methods in Computer-Aided Design, 2024

2023

Harnessing Multiple BMC Engines Together for Efficient Formal Verification.

Devleena Ghosh, Sumana Ghosh, Raj Kumar Gajavelly, Ansuman Banerjee

Proceedings of the 21st ACM-IEEE International Symposium on Formal Methods and Models for System Design, 2023

2019

Input Elimination Transformations for Scalable Verification and Trace Reconstruction.

Raj Kumar Gajavelly, Jason Baumgartner, Alexander Ivrii, Robert L. Kanzelman, Shiladitya Ghosh

Proceedings of the 2019 Formal Methods in Computer Aided Design, 2019

2017

Symbolic trajectory evaluation for word-level verification: theory and implementation.

Supratik Chakraborty, Zurab Khasidashvili, Carl-Johan H. Seger, Rajkumar Gajavelly, Tanmay Haldankar, Dinesh Chhatani, Rakesh Mistry

Formal Methods Syst. Des., 2017

2016

The art of semi-formal bug hunting.

Pradeep Kumar Nalla, Raj Kumar Gajavelly, Jason Baumgartner, Hari Mony, Robert Kanzelman, Alexander Ivrii

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Word-Level Symbolic Trajectory Evaluation.

Supratik Chakraborty, Zurab Khasidashvili, Carl-Johan H. Seger, Rajkumar Gajavelly, Tanmay Haldankar, Dinesh Chhatani, Rakesh Mistry

Proceedings of the Computer Aided Verification - 27th International Conference, 2015

2014

Effective Liveness Verification Using a Transformation-Based Framework.

Pradeep Kumar Nalla, Raj Kumar Gajavelly, Hari Mony, Jason Baumgartner, Robert Kanzelman

Proceedings of the 2014 27th International Conference on VLSI Design, 2014