Swamy D. Ponpandi

According to our database1, Swamy D. Ponpandi authored at least 9 papers between 2011 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2017
Shaping data for application performance and energy optimization in dynamic data view framework.
Integr., 2017

2015
Dynamic Data Shapers Optimize Performance in Dynamic Binary Optimization (DBO) Environment.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015

2014
A placer for composable FPGA with 2D mesh network.
Int. J. Embed. Syst., 2014

User satisfaction aware routing and energy modeling of polymorphic network on chip architecture.
Comput. Electr. Eng., 2014

An Evaluation of User Satisfaction Driven Scheduling in a Polymorphic Embedded System.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

2013
PolyNOC - A polymorphic thread simulator for NoC communication based embedded systems.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

User satisfaction aware routing decisions in NOC.
Proceedings of the Network on Chip Architectures, 2013

2011
Partial reconfiguration logic synthesis by temporal slicing.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

A novel thread scheduler design for polymorphic embedded systems.
Proceedings of the 14th International Conference on Compilers, 2011


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