Tadayoshi Horita

According to our database1, Tadayoshi Horita authored at least 24 papers between 1995 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement.
Trans. Computational Science, 2016

2015
An FPGA-Based Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Perceptron (Full Version).
Trans. Computational Science, 2015

2014
Multilayer Perceptrons Which Are Tolerant to Multiple Faults and Learnings to Realize Them.
Trans. Computational Science, 2014

A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

2013
An FPGA-based multiple-weight-and-neuron-fault tolerant digital multilayer perceptron.
Neurocomputing, 2013

2012
A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement.
Proceedings of the IEEE 18th Pacific Rim International Symposium on Dependable Computing, 2012

2011
An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications.
Trans. Computational Science, 2011

2010
An FPGA-based fast classifier with high generalization property.
SIGARCH Computer Architecture News, 2010

2009
Novel Value Injection Learning Methods Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

An Implementation of a Fault-Tolerant 2D Systolic Array on FPGAs and Its Evaluation.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

A Computer Cluster for Tests of Parallel Programming Environments Including Operating Systems.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

2008
Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant.
IEICE Transactions, 2008

An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches.
IEICE Transactions, 2008

2006
A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2001
Analytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

2000
Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions.
IEEE Trans. Computers, 2000

A System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

A System for Efficiently Self-Reconstructing E-1½-Track Switch Torus Arrays.
Proceedings of the 5th International Symposium on Parallel Architectures, 2000

1999
Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions.
Proceedings of the 1999 International Symposium on Parallel Architectures, 1999

1997
A built-in self-reconfigurable scheme for 3D mesh arrays.
Proceedings of the 1997 International Symposium on Parallel Architectures, 1997

A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults.
Proceedings of the 1997 International Symposium on Parallel Architectures, 1997

Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996
Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995
Reconfigurable architectures for mesh-arrays with PE and link faults.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995


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