Itsuo Takanami

According to our database1, Itsuo Takanami authored at least 93 papers between 1976 and 2019.

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Bibliography

2019
A Built-In Circuit for Self-reconfiguring Mesh-Connected Processor Arrays with Spares on Diagonal.
Trans. Computational Science, 2019

2018
Restructuring Mesh-Connected Processor Arrays with Spares on Four Sides by Orthogonal Side Rotation.
Proceedings of the 23rd IEEE Pacific Rim International Symposium on Dependable Computing, 2018

Degradable Restructuring of Mesh-Connected Processor Arrays with Spares on Orthogonal Sides.
Proceedings of the 23rd IEEE Pacific Rim International Symposium on Dependable Computing, 2018

2017
A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays with Spares on Diagonal.
Proceedings of the 22nd IEEE Pacific Rim International Symposium on Dependable Computing, 2017

2016
A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement.
Trans. Computational Science, 2016

2015
An FPGA-Based Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Perceptron (Full Version).
Trans. Computational Science, 2015

2014
Multilayer Perceptrons Which Are Tolerant to Multiple Faults and Learnings to Realize Them.
Trans. Computational Science, 2014

A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings.
Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

2013
An FPGA-based multiple-weight-and-neuron-fault tolerant digital multilayer perceptron.
Neurocomputing, 2013

2012
A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement.
Proceedings of the IEEE 18th Pacific Rim International Symposium on Dependable Computing, 2012

2011
An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications.
Trans. Computational Science, 2011

2010
An FPGA-based fast classifier with high generalization property.
SIGARCH Computer Architecture News, 2010

2009
Novel Value Injection Learning Methods Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

An Implementation of a Fault-Tolerant 2D Systolic Array on FPGAs and Its Evaluation.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2009

2008
Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant.
IEICE Transactions, 2008

An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches.
IEICE Transactions, 2008

2006
A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2004
Self-Reconfiguring of 1½-Track-Switch Mesh Arrays with Spares on One Row and One Column by Simple Built-in Circuit.
IEICE Transactions, 2004

2002
An Extreme Value Injection Approach with Reduced Learning Time to Make MLNs Multiple-Weight-Fault Tolerant.
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002

2001
Analytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001

Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare Replacement.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions.
IEEE Trans. Computers, 2000

A System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

A System for Efficiently Self-Reconstructing E-1½-Track Switch Torus Arrays.
Proceedings of the 5th International Symposium on Parallel Architectures, 2000

A Fault-Value Injection Approach for Multiple-Weight-Fault Tolerance of MNNs.
Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, 2000

Built-in Self-Reconfiguring Systems for Mesh-Connected Processor Arrays with Spares on Two Rows/Columns.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999
Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions.
Proceedings of the 1999 International Symposium on Parallel Architectures, 1999

1997
A built-in self-reconfigurable scheme for 3D mesh arrays.
Proceedings of the 1997 International Symposium on Parallel Architectures, 1997

A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults.
Proceedings of the 1997 International Symposium on Parallel Architectures, 1997

Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

On fault injection approaches for fault tolerance of feedforward neural networks.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995
Optimal Simulation of Two-Dimensional Alternating Finite Automata by Three-Way Nondeterministic Turing Machines.
Theor. Comput. Sci., 1995

Cooperating Systems of Three-Way, Two-Dimensional Finite Automata.
IJPRAI, 1995

The Effect of Inkdots for Two-Dimensional Automata.
IJPRAI, 1995

Reconfigurable architectures for mesh-arrays with PE and link faults.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994
On 1-inkdot Alternating Turing Machines with Small Space.
Theor. Comput. Sci., 1994

Simulation of Three-Dimensional One-Marker Automata by Five-Way Turing Machines.
Inf. Sci., 1994

Constant Leaf-Size Hierarchy of Two-Dimensional Alternating Turing Machines.
IJPRAI, 1994

A Characterization of Recognizable Picture Languages.
IJPRAI, 1994

1993
Construction of fault-tolerant mesh-connected highly parallel computer and its performance analysis.
Systems and Computers in Japan, 1993

A note on three-dimensional alternating Turing machines with space smaller than log m.
Inf. Sci., 1993

A Note on Multi-Inkdot Nondeterministic Turing Machines with Small Space.
Inf. Process. Lett., 1993

1992
A Relationship Between Nondeterministic Turing Machines and 1-Inkdot Turing Machines with Small Space.
Inf. Process. Lett., 1992

Two Topics Concerning Two-Dimensional Automata Operating in Parallel.
IJPRAI, 1992

On the Power of One-Way Synchronized Alternating Machines with Small Space.
Int. J. Found. Comput. Sci., 1992

Constant Leaf-Size Hierarchy of Two-Dimensional Alternating Turing Machines.
Proceedings of the Parallel Image Analysis, Second International Conference, 1992

1991
A Note on Real-Time One-Way Alternating Multicounter Machines.
Theor. Comput. Sci., 1991

A survey of two-dimensional automata theory.
Inf. Sci., 1991

Alternating Turing Machines with Modified Accepting Structure.
Int. J. Found. Comput. Sci., 1991

1990
A note on time-bounded bottom-up pyramid cellular acceptors.
Inf. Sci., 1990

1989
Complexity of Acceptance Problems for Two-Dimensional Automata.
Proceedings of the A Perspective in Theoretical Computer Science, 1989

The Simulation of Two-Dimensional One-Marker Automata by Three-Way Turing Machines.
Proceedings of the Array Grammars, Patterns and Recognizers, 1989

Deterministic Two-Dimensional On-Line Tessellation Acceptors are Equivalent to Two-Way Two-Dimensional Alternating Finite Automata Through 180°-Rotation.
Theor. Comput. Sci., 1989

A Leaf-Size Hierarchy of Two-Dimensional Alternating Turing Machines.
Theor. Comput. Sci., 1989

One-Dimensional Bounded Cellular Acceptor with Rotated Inputs. A Relationship between ∧ and ∨ Types.
Systems and Computers in Japan, 1989

Lower Bounds for Language Recognition on Two-Dimensional Alternating Multihead Machines.
J. Comput. Syst. Sci., 1989

The Simulation of Two-Dimensional One-Marker Automata by Three-Way Turing Machines.
IJPRAI, 1989

1988
A note on three-way two-dimensional alternating Turing machines.
Inf. Sci., 1988

Some Considerations About NPRIORITY(1) Without ROM.
Inf. Process. Lett., 1988

1987
One-dimensional bounded cellular acceptor with rotated inputs.
Systems and Computers in Japan, 1987

Hierarchical properties of the κ -neighborhood template A-type 2-dimensional bounded cellular acceptor.
Systems and Computers in Japan, 1987

1986
Relationship between the accepting powers of (k, l)-neighborhood template δ-type one-dimensional bounded cellular acceptors and other types of two-dimensional automata.
Systems and Computers in Japan, 1986

Relationships of accepting powers between cellular space with bounded number of state-changes and other automata.
Systems and Computers in Japan, 1986

Three-way two-dimensional finite automata with rotated inputs.
Inf. Sci., 1986

1985
Alternating Simple Multihead Finite Automata.
Theor. Comput. Sci., 1985

Alternating On-Line Turing Machines with Only Universal States and Small Space Bounds.
Theor. Comput. Sci., 1985

A space-hierarchy result on two-dimensional alternating Turing machines with only universal states.
Inf. Sci., 1985

1983
Two-Dimensional Pattern Matching by Two-Dimensional on-Line Tessellation Acceptors.
Theor. Comput. Sci., 1983

Two-Dimensional Alternating Turing Machines.
Theor. Comput. Sci., 1983

A Relationship between Two-Dimensional Finite Automata and Three-Way Tape-Bounded Two-Dimensional Turing Machines.
Theor. Comput. Sci., 1983

Two-dimensional automata with rotated inputs (projection-type).
Inf. Sci., 1983

Connected pictures are not recognizable by deterministic two-dimensional on-line tessellation acceptors.
Computer Vision, Graphics, and Image Processing, 1983

1982
A note on three-dimensional finite automata.
Inf. Sci., 1982

A note on rebound automata.
Inf. Sci., 1982

A Note on Alternating On-Line Turing Machines.
Inf. Process. Lett., 1982

Two-Dimensional Alternating Turing Machines with Only Universal States
Information and Control, 1982

1980
Two-dimensional automata with rotated inputs.
Inf. Sci., 1980

Nonclosure property of nondeterministic two-dimensional finite automata under cyclic closure.
Inf. Sci., 1980

Errata: Corrections to two papers.
Inf. Sci., 1980

A note on deterministic three-way tape-bounded two-dimensional Turing machines.
Inf. Sci., 1980

A Note on Decision Problems for Three-Way Two-Dimensional Finite Automata.
Inf. Process. Lett., 1980

1979
One-Way Simple Multihead Finite Automata.
Theor. Comput. Sci., 1979

On-line n-bounded multicounter automata.
Inf. Sci., 1979

Three-way tape-bounded two-dimensional turing machines.
Inf. Sci., 1979

Closure properties of three-way and four-way tape-bounded two-dimensional turing machines.
Inf. Sci., 1979

Three-way two-dimensional multicounter automata.
Inf. Sci., 1979

A Note on Bottom-Up Pyramid Acceptors.
Inf. Process. Lett., 1979

A Note on Cyclic Closure Operations.
Inf. Process. Lett., 1979

1978
Cyclic closure properties of automata on a two-dimensional tape.
Inf. Sci., 1978

A note on closure properties of the classes of sets accepted by tape-bounded two-dimensional turing machines.
Inf. Sci., 1978

A Note on Two-Dimensional Finite Automata.
Inf. Process. Lett., 1978

1976
General Results on Tour Lengths in Machines and Digraphs.
SIAM J. Comput., 1976


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