Taegun Yim

Orcid: 0000-0002-1732-842X

According to our database1, Taegun Yim authored at least 10 papers between 2017 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
A Separated Pre-Charge Sense Amplifier With Fast Sensing, Low Power, Small Area, and High Reliability for Hybrid MTJ/CMOS Logic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., June, 2026

A Compact Low-Voltage and Low-Power Flip-Flop with Static, Contention-Free, and Redundant-Transition-Free Operation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025
Single-Ended Back-Bias Voltage Generator Using One Pumping Capacitor.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2025

2023
A picowatt CMOS voltage reference with 0.046 %/V line sensitivity for a low-power IoT system.
Proceedings of the 20th International SoC Design Conference, 2023

2021
A High Speed Modified Dickson Charge Pump.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2018
A Low-Voltage Charge Pump with High Pumping Efficiency.
Proceedings of the TENCON 2018, 2018

Low-Energy Consumption Write Circuit using Comparing Operation in STT-MRAM.
Proceedings of the TENCON 2018, 2018

Bit-line Sense Amplifier Using PMOS Charge Transfer Pre-amplifier for Low-Voltage DRAM.
Proceedings of the TENCON 2018, 2018

2017
Energy-efficient write circuit in STT-MRAM based look-up table (LUT) using comparison write scheme.
Proceedings of the International SoC Design Conference, 2017

Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA.
Proceedings of the International SoC Design Conference, 2017


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