Hongil Yoon
According to our database1,
Hongil Yoon
authored at least 31 papers
between 1997 and 2023.
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Bibliography
2023
A picowatt CMOS voltage reference with 0.046 %/V line sensitivity for a low-power IoT system.
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
2021
Proceedings of the 2021 USENIX Annual Technical Conference, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
2018
Proceedings of the TENCON 2018, 2018
Proceedings of the TENCON 2018, 2018
Bit-line Sense Amplifier Using PMOS Charge Transfer Pre-amplifier for Low-Voltage DRAM.
Proceedings of the TENCON 2018, 2018
Proceedings of the TENCON 2018, 2018
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018
2017
Variation-Tolerant Sensing Circuit for Ultralow-Voltage Operation of Spin-Torque Transfer Magnetic RAM.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Energy-efficient write circuit in STT-MRAM based look-up table (LUT) using comparison write scheme.
Proceedings of the International SoC Design Conference, 2017
Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA.
Proceedings of the International SoC Design Conference, 2017
2016
Variation-tolerant and low power look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile field programmable gate array (FPGA).
Proceedings of the International SoC Design Conference, 2016
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
2013
IEICE Electron. Express, 2013
2012
Integration of dual channel timing formatter system for high speed memory test equipment.
Proceedings of the International SoC Design Conference, 2012
2007
Design and Implementation of MIMO-OFDM Baseband Processor for High-Speed Wireless LANs.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
High Speed, Minimal Area, and Low Power SEC Code for DRAMs with Large I/O Data Widths.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
Investigation of manufacturing variations of planar InP/InGaAs avalanche photodiodes for optical receivers.
Microelectron. J., 2004
An In-Order SMT Architecture with Static Resource Partitioning for Consumer Applications.
Proceedings of the Parallel and Distributed Computing: Applications and Technologies, 2004
2003
New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications.
IEEE Trans. Consumer Electron., 2003
A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor.
IEEE J. Solid State Circuits, 2003
1999
IEEE J. Solid State Circuits, 1999
1998
A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme.
IEEE J. Solid State Circuits, 1998
A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system.
IEEE J. Solid State Circuits, 1998
1997
IEEE J. Solid State Circuits, 1997