Choong Keun Lee

According to our database, Choong Keun Lee authored at least 8 papers between 2012 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A picowatt CMOS voltage reference with 0.046 %/V line sensitivity for a low-power IoT system.

Hyeongjun Kim, Taegun Yim, Choong Keun Lee, Hongil Yoon

Proceedings of the 20th International SoC Design Conference, 2023

2021

A High Speed Modified Dickson Charge Pump.

Taegun Yim, Choong Keun Lee, Hongil Yoon

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2018

A Low-Voltage Charge Pump with High Pumping Efficiency.

Taegun Yim, Seungjin Lee, Choong Keun Lee, Hongil Yoon

Proceedings of the TENCON 2018, 2018

Bit-line Sense Amplifier Using PMOS Charge Transfer Pre-amplifier for Low-Voltage DRAM.

Choong Keun Lee, Taegun Yim, Hongil Yoon

Proceedings of the TENCON 2018, 2018

A New Charge Pump Switch Parallel to Series Connection.

SeoungMin Lee, Choong Keun Lee, Hongil Yoon

Proceedings of the TENCON 2018, 2018

2017

Energy-efficient write circuit in STT-MRAM based look-up table (LUT) using comparison write scheme.

Seungjin Lee, Taegun Yim, Choong Keun Lee, Kyungseon Cho, Hongil Yoon

Proceedings of the International SoC Design Conference, 2017

Low power multi-context look-up table (LUT) using spin-torque transfer magnetic RAM for non-volatile FPGA.

Kyungseon Cho, Seungjin Lee, Choong Keun Lee, Taegun Yim, Hongil Yoon

Proceedings of the International SoC Design Conference, 2017

2012

Integration of dual channel timing formatter system for high speed memory test equipment.

Jaeseok Park, Ingeol Lee, Young-Seok Park, Sung-Geun Kim, Kyungho Ryu, Dong-Hoon Jung, Kangwook Jo, Choong Keun Lee, Hongil Yoon, Seong-Ook Jung, Woo-Young Choi, Sungho Kang

Proceedings of the International SoC Design Conference, 2012