Taeseung Kang

According to our database, Taeseung Kang authored at least 3 papers in 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 96-Gb/s 1.6-V_ppd PAM-8 Transmitter With High-Swing and Low-Loading Cascaded Driver in 40-nm CMOS Technology.

Taeseung Kang, Jeonghyu Yang, Eunji Song, Seungwoo Son, Hyuntae Kim, Jaeduk Han

IEEE Trans. Very Large Scale Integr. Syst., July, 2025

Process-Portable Layout Generation of High-Speed Digital Circuit Using Standard Cells in FinFET.

Taeseung Kang, Taeho Shin, Heejun Kim, Jaeduk Han

Proceedings of the 21st International Conference on Synthesis, 2025

A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology.

Yunseong Jo, Taeseung Kang, Jeonghyu Yang, Jaeduk Han

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025