Taewoo Han

Orcid: 0009-0005-1636-7290

Affiliations:
  • Samsung Electronics, Department of SOC Design Team, Gyeonggi-do, South Korea
  • Yonsei University, Department of Electrical and Electronic Engineering, Seoul, South Korea (PhD 2015)


According to our database1, Taewoo Han authored at least 9 papers between 2009 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2017
An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time.
IEEE Trans. Computers, 2017

2016
Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2015
Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2014
A novel test access mechanism for parallel testing of multi-core system.
IEICE Electron. Express, 2014

A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Bit transmission error correction scheme for FlexRay based automotive communication systems.
Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

2011
Path search engine for fast optimal path search using efficient hardware architecture.
Proceedings of the International SoC Design Conference, 2011

2010
An Advanced BIRA for Memories With an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009
An Effective Programmable Memory BIST for Embedded Memory.
IEICE Trans. Inf. Syst., 2009


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