Sungho Kang

Tae-Hyun Kim

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

A New Fail Address Memory Architecture for Cost-Effective ATE.

[BibT_eX]

[DOI]

Sooryeong Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024

2023

STRAIT: Self-Test and Self-Recovery for AI Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

TRUST: Through-Silicon via Repair Using Switch Matrix Topology.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

TSV Built-In Self-Repair Architecture for Improving the Yield and Reliability of HBM.

[BibT_eX]

[DOI]

Youngkwang Lee

Donghyun Han

IEEE Trans. Very Large Scale Integr. Syst., April, 2023

Shift Left Quality Management System (QMS) Using a 3-D Matrix Scanning Method on System on a Chip.

[BibT_eX]

[DOI]

Yong Lee

IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

Novel Error-Tolerant Voltage-Divider-Based Through-Silicon-Via Test Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Scan Chain Architecture With Data Duplication for Multiple Scan Cell Fault Diagnosis.

[BibT_eX]

[DOI]

Sunghoon Kim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

GPU-Based Redundancy Analysis using Partitioning Method for Memory Repair.

[BibT_eX]

[DOI]

Proceedings of the 20th International SoC Design Conference, 2023

Redundancy Analysis Simplification Scheme for High-Speed Memory Repair.

[BibT_eX]

[DOI]

Proceedings of the 20th International SoC Design Conference, 2023

LOTS: Low Overhead TSV Repair Method Using IEEE-1838 Standard Architecture.

[BibT_eX]

[DOI]

Proceedings of the 20th International SoC Design Conference, 2023

2022

ECMO: ECC Architecture Reusing Content-Addressable Memories for Obtaining High Reliability in DRAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2022

Scan Cell Modification for Intra Cell-Aware Scan Chain Diagnosis.

[BibT_eX]

[DOI]

Hyojoon Yun

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Herringbone-Based TSV Architecture for Clustered Fault Repair and Aging Recovery.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Hybrid Test Scheme for Automotive IC in Multisite Testing.

[BibT_eX]

[DOI]

Hyojoon Yun

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Reduced-Pin-Count BOST for Test-Cost Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Multibank Optimized Redundancy Analysis Using Efficient Fault Collection.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

SPAR: A New Test-Point Insertion Using Shared Points for Area Overhead Reduction.

[BibT_eX]

[DOI]

Gyungbin Kim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

An Improved Early Termination Methodology Using Convolutional Neural Network.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

FAME: Fault Address Memory Structure for Repair Time Reduction.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

PROG: Per-Row Output Generator for BOST.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

ZOS: Zero Overhead Scan for Systolic Array-based AI accelerator.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

2021

Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs.

[BibT_eX]

[DOI]

Jungil Mok

IEEE Trans. Very Large Scale Integr. Syst., 2021

Low-Power Scan Correlation-Aware Scan Cluster Reordering for Wireless Sensor Networks.

[BibT_eX]

[DOI]

Sensors, 2021

A Secure Scan Architecture Protecting Scan Test and Scan Dump Using Skew-Based Lock and Key.

[BibT_eX]

[DOI]

Hyungil Woo

IEEE Access, 2021

An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process.

[BibT_eX]

[DOI]

IEEE Access, 2021

On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug.

[BibT_eX]

[DOI]

IEEE Access, 2021

A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs.

[BibT_eX]

[DOI]

IEEE Access, 2021

Reconfigurable Scan Architecture for High Diagnostic Resolution.

[BibT_eX]

[DOI]

Jihye Kim

IEEE Access, 2021

ECC-Aware Fast and Reliable Pattern Matching Redundancy Analysis for Highly Reliable Memory.

[BibT_eX]

[DOI]

IEEE Access, 2021

Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory.

[BibT_eX]

[DOI]

Donghyun Han

IEEE Access, 2021

Post-bond Repair of Line Faults with Double-bit ECC for 3D Memory.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

An Effective Spare Allocation Methodology for 3D Memory Repair with BIRA.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Area Efficient Built-In Redundancy Analysis using Pre-Solutions with Various Spare Structure.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

A Circular-based TSV Repair Architecture.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Hardware Efficient Built-in Self-test Architecture for Power and Ground TSVs in 3D IC.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

2020

GPU-Based Redundancy Analysis Using Concurrent Evaluation.

[BibT_eX]

[DOI]

Tae Hyun Kim

IEEE Trans. Very Large Scale Integr. Syst., 2020

A New Logic Topology-Based Scan Chain Stitching for Test-Power Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst., 2020

Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults.

[BibT_eX]

[DOI]

Ingeol Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Fine-Grained Defect Diagnosis for CMOL FPGA Circuits.

[BibT_eX]

[DOI]

IEEE Access, 2020

Fail Memory Configuration Set for RA Estimation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

W-ERA: One-Time Memory Repair with Wafer-Level Early Repair Analysis for Cost Reduction.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2020

Redundancy Analysis Optimization with Clustered Known Solutions for High Speed Repair.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2020

Memory-like Defect Diagnosis for CMOL FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2020

2019

Dynamic Built-In Redundancy Analysis for Memory Repair.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Test-Friendly Data-Selectable Self-Gating (DSSG).

[BibT_eX]

[DOI]

Jihye Kim

Sangjun Lee

IEEE Trans. Very Large Scale Integr. Syst., 2019

Highly Reliable Redundant TSV Architecture for Clustered Faults.

[BibT_eX]

[DOI]

Ingeol Lee

IEEE Trans. Reliab., 2019

TSV Repair Architecture for Clustered Faults.

[BibT_eX]

[DOI]

Jaewon Jang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Tunable Compact Probing Detector with Fast Analysis Time Against Invasive Attacks.

[BibT_eX]

[DOI]

Proceedings of the 2019 International SoC Design Conference, 2019

Redundancy Analysis based on Fault Distribution for Memory with Complex Spares.

[BibT_eX]

[DOI]

Proceedings of the 2019 International SoC Design Conference, 2019

Transition-delay Test Methodology for Designs with Self-gating.

[BibT_eX]

[DOI]

Proceedings of the 2019 International SoC Design Conference, 2019

A New Scan Chain Reordering Method for Low Power Consumption based on Care Bit Density.

[BibT_eX]

[DOI]

Proceedings of the 2019 International SoC Design Conference, 2019

2018

An Area-Efficient BIRA With 1-D Spare Segments.

[BibT_eX]

[DOI]

Donghyun Kim

IEEE Trans. Very Large Scale Integr. Syst., 2018

Fast Built-In Redundancy Analysis Based on Sequential Spare Line Allocation.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2018

Thermal Aware Test Scheduling for NTV Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Fault Group Pattern Matching With Efficient Early Termination for High-Speed Redundancy Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

3D Memory Formed of Unrepairable Memory Dice and Spare Layer.

[BibT_eX]

[DOI]

Proceedings of the TENCON 2018, 2018

Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2018

Low Power Scan Chain Architecture Based on Circuit Topology.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2018

2017

Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

FRESH: A New Test Result Extraction Scheme for Fast TSV Tests.

[BibT_eX]

[DOI]

Hyunyul Lim

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs.

[BibT_eX]

[DOI]

Young-Woo Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores.

[BibT_eX]

[DOI]

Inhyuk Choi

IEEE Trans. Computers, 2017

Proof of Concept of Home IoT Connected Vehicles.

[BibT_eX]

[DOI]

Younsun Kim

Sensors, 2017

Reconfigurable scan architecture for test power and data volume reduction.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

A novel X-filling method for capture power reduction.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

A selective error data capture method using on-chip DRAM for silicon debug of multi-core design.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2017

A new repair scheme for TSV-based 3D memory using base die repair cells.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2017

2016

Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression.

[BibT_eX]

[DOI]

Sungyoul Seo

Yong Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A New 3-D Fuse Architecture to Improve Yield of 3-D Memories.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Process variation-aware bridge fault analysis.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

Discussion of cost-effective redundancy architectures.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2016

A new online test and debug methodology for automotive camera image processing system.

[BibT_eX]

[DOI]

Inhyuk Choi

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

Test access mechaism for stack test time reduction of 3-dimensional integrated circuit.

[BibT_eX]

[DOI]

Inhyuk Choi

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

A Novel Massively Parallel Testing Method Using Multi-Root for High Reliability.

[BibT_eX]

[DOI]

Haksong Kim

Yong Lee

IEEE Trans. Reliab., 2015

A scan shifting method based on clock gating of multiple groups for low power scan testing.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Low power scan bypass technique with test data reduction.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2011

A Memory-Efficient Bit-Split Parallel String Matching Using Pattern Dividing for Intrusion Detection Systems.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2011

A Lossless Color Image Compression Architecture Using a Parallel Golomb-Rice Hardware CODEC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2011

Communication-aware task scheduling and voltage selection for total energy minimization in a multiprocessor system using Ant Colony Optimization.

[BibT_eX]

[DOI]

Inf. Sci., 2011

2010

A Fast IP Address Lookup Algorithm Based on Search Space Reduction.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2010

Selective Scan Slice Grouping Technique for Efficient Test Data Compression.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2010

A Selective Scan Chain Activation Technique for Minimizing Average and Peak Power Consumption.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2010

A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2010

A Pattern Partitioning Algorithm for Memory-Efficient Parallel String Matching in Deep Packet Inspection.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2010

A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2010

A high performance network-on-chip scheme using lossless data compression.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2010

A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2010

A Pattern Group Partitioning for Parallel String Matching using a Pattern Grouping Metric.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2010

2009

Grouped Scan Slice Repetition Method for Reducing Test Data Volume and Test Application Time.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2009

Selective scan slice repetition for simultaneous reduction of test power consumption and test data volume.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2009

A memory-efficient parallel string matching for intrusion detection systems.

[BibT_eX]

[DOI]

IEEE Commun. Lett., 2009

A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

FPGA-based verification methodology of SoC-type CMOS image signal processor.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2008

Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Ant colony based efficient triplet calculation methodology for arithmetic built-in self test.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2008

An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment.

[BibT_eX]

[DOI]

Michael S. Hsiao

J. Electron. Test., 2008

An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

An Effective Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-Based Scheme.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs.

[BibT_eX]

[DOI]

Sunghoon Chun

J. Electron. Test., 2007

High-MDSI: A High-level Signal Integrity Fault Test Pattern Generation Method for Interconnects.

[BibT_eX]

[DOI]

Sunghoon Chun

Proceedings of the 16th Asian Test Symposium, 2007

2006

MICRO: a new hybrid test data compression/decompression scheme.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Increasing encoding efficiency of LFSR reseeding-based test compression.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

An Efficient Dictionary Organization for Maximum Diagnosis.

[BibT_eX]

[DOI]

J. Electron. Test., 2006

System on a Chip Implementation of Social Insect Behavior for Adaptive Network Routing.

[BibT_eX]

[DOI]

Proceedings of the Computational Intelligence, 2006

An Effective Test Pattern Generation for Testing Signal Integrity.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

2005

A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

A new maximal diagnosis algorithm for interconnect test.

[BibT_eX]

[DOI]

Hyun-Don Kim

IEEE Trans. Very Large Scale Integr. Syst., 2004

An Acceleration Processor for Data Intensive Scientific Computing.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2004

2003

Test-decompression mechanism using a variable-length multiple-polynomial LFSR.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

A New Maximal Diagnosis Algorithm for Bus-structured Systems.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

DPSC SRAM Transparent Test Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

A new multiple weight set calculation algorithm.

[BibT_eX]

[DOI]

Jin-kyue Lee

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A Heuristic for Multiple Weight Set Generation.

[BibT_eX]

[DOI]

Jin-kyue Lee

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

1999

An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment.

[BibT_eX]

[DOI]

Jongchul Shin

Proceedings of the IEEE International Conference On Computer Design, 1999

At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks.

[BibT_eX]

[DOI]

Jongchul Shin