Tai-Haur Kuo

Orcid: 0000-0002-5477-0583

According to our database1, Tai-Haur Kuo authored at least 61 papers between 1993 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A 3mW 2.7GS/s 8b Subranging ADC with Multiple-Reference-Reference-Embedded Comparators.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier.
IEEE J. Solid State Circuits, 2022

A 0.4-mA-Quiescent-Current, 0.00091%-THD+N Class-D Audio Amplifier With Low-Complexity Frequency Equalization for PWM-Residual- Aliasing Reduction.
IEEE J. Solid State Circuits, 2022

Fixed-Switching-Frequency Background Capacitor-Current-Sensor Calibration for DC-DC Converters.
IEEE J. Solid State Circuits, 2022

A 9.8-fJ/conv.-step FoMW 8b 2.5-GS/s Single-Channel CDAC-Assisted Subranging ADC with Reference-Embedded Comparators.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 0.82mW 14b 130MS/S Pipelined-SAR ADC With a Distributed Averaging Correlated Level Shifting (DACLS) Ringamp and Bypass-Window Backend.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

A 121dB DR, 0.0017% THD+N, 8× Jitter-Effect Reduction Digital-Input Class-D Audio Amplifier with Supply-Voltage-Scaling Volume Control and Series-Connected DSM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2021
A 3 mW 6-bit 4 GS/s Subranging ADC With Subrange-Dependent Embedded References.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR >64/50 dBc Over the First/Second Nyquist Zone.
IEEE J. Solid State Circuits, 2021

Self-powered light sensor for simultaneous intensity-and-direction sensing and maximum-energy harvesting with shared photodiodes.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
A Reconfigurable Transient Optimizer Applied to a Four-Phase Buck Converter for Optimizing Both DVS and Load Transient Responses.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Calibration-Free 14-b 0.7-mW 100-MS/s Pipelined-SAR ADC Using a Weighted- Averaging Correlated Level Shifting Technique.
IEEE J. Solid State Circuits, 2020

A 0.07-mm<sup>2</sup> 162-mW DAC Achieving >65 dBc SFDR and < -70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing.
IEEE J. Solid State Circuits, 2020

A Reconfigurable and Extendable Single-Inductor Single-Path Three-Switch Converter for Indoor Photovoltaic Energy Harvesting.
IEEE J. Solid State Circuits, 2020

A 177mW 10GS/s NRZ DAC with Switching-Glitch Compensation Achieving > 64dBc SFDR and < -77dBc IM3.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

16.4 A Calibration-Free 71.7dB SNDR 100MS/s 0.7mW Weighted-Averaging Correlated Level Shifting Pipelined SAR ADC with Speed-Enhancement Scheme.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

23.5 A 0.41mA Quiescent Current, 0.00091% THD+N Class-D Audio Amplifier with Frequency Equalization for PWM-Residual-Aliasing Reduction.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 12-Bit Time-Interleaved 400-MS/s Pipelined ADC With Split-ADC Digital Background Calibration in 4, 000 Conversions/Channel.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

An Analog Optimum Torque Control IC for a 200-W Wind Energy Harvesting System.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 75.3-dB SNDR 24-MS/s Ring Amplifier-Based Pipelined ADC Using Averaging Correlated Level Shifting and Reference Swapping for Reducing Errors From Finite Opamp Gain and Capacitor Mismatch.
IEEE J. Solid State Circuits, 2019

A 0.07mm<sup>2</sup> 210mW Single-1.1V-Supply 14-bit 10GS/s DAC with Concentric Parallelogram Routing and Output Impedance Compensation.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A 15-bit 20 MS/s SHA-Less Pipelined ADC Achieving 73.7 dB SNDR with Averaging Correlated Level Shifting Technique.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

A Light Energy Harvesting Single-Inductor Dual-Input Dual-Output Converter for WSN.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

Background Capacitor-Current-Sensor Calibration of DC-DC Buck Converter with DVS for Accurately Accelerating Load-Transient Response.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 3mW 6b 4GS/s Subranging ADC with Adaptive Offset-Adjustable Comparators.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 40/30 MS/s Dual-Mode Pipelined ADC with Error Averaging Techniques in 90nm CMOS Achieving 71.2/74.5 dB SNDR over the Entire Nyquist Bandwidth.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 100-pA Adaptive-FOCV MPPT Circuit with >99.6% Tracking Efficiency for Indoor Light Energy Harvesting.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
Introduction to the Special Issue on the 2018 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2018

A Four-Phase Buck Converter With Capacitor-Current-Sensor Calibration for Load-Transient-Response Optimization That Reduces Undershoot/Overshoot and Shortens Settling Time to Near Their Theoretical Limits.
IEEE J. Solid State Circuits, 2018

A Low Quiescent Current, Low THD+N Class-D Audio Amplifier With Area-Efficient PWM-Residual-Aliasing Reduction.
IEEE J. Solid State Circuits, 2018

A 0.96mA quiescent current, 0.0032% THD+N, 1.45W Class-D audio amplifier with area-efficient PWM-residual-aliasing reduction.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2016
A Single-Inductor Dual-Path Three-Switch Converter With Energy-Recycling Technique for Light Energy Harvesting.
IEEE J. Solid State Circuits, 2016

A 2.4 mA Quiescent Current, 1 W Output Power Class-D Audio Amplifier With Feed-Forward PWM-Intermodulated-Distortion Reduction.
IEEE J. Solid State Circuits, 2016

12.6 Capacitor-current-sensor calibration technique and application in a 4-phase buck converter with load-transient optimization.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A Monolithic Capacitor-Current-Controlled Hysteretic Buck Converter With Transient-Optimized Feedback Circuit.
IEEE J. Solid State Circuits, 2015

20.9 An energy-recycling three-switch single-inductor dual-input buck/boost DC-DC converter with 93% peak conversion efficiency and 0.5mm<sup>2</sup> active area for light energy harvesting.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

An undershoot/overshoot-suppressed current-mode buck converter with voltage-setting control for type-II compensator.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < -61dB at 2.8 GS/s With DEMDRZ Technique.
IEEE J. Solid State Circuits, 2014

An analog optimum torque control IC for a 200W wind energy conversion system with over 99% MPPT accuracy, 1.7% THDi and 0.99 power factor.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

An open-loop class-D audio amplifier with increased low-distortion output power and PVT-insensitive EMI reduction.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

A current-mode buck converter with bandwidth reconfigurable for enhanced efficiency and improved load transient response.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
An adaptive load-line tuning IC for photovoltaic module integrated mobile device with 470µs transient time, over 99% steady-state accuracy and 94% power conversion efficiency.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over entire Nyquist bandwidth.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Optimal Design for Delta-Sigma Modulators With Root Loci Inside Unit Circle.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A 100 W 5.1-Channel Digital Class-D Audio Amplifier With Single-Chip Design.
IEEE J. Solid State Circuits, 2012

A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection.
IEEE J. Solid State Circuits, 2012

2011
Leading-Subcycles Capacitor Error-Averaging Scheme for Cyclic ADCs.
IEEE Trans. Instrum. Meas., 2011

2010
Bias-and-Input Interchanging Technique for Cyclic/Pipelined ADCs With Opamp Sharing.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

2009
Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

2008
Capacitor-Swapping Cyclic A/D Conversion Techniques With Reduced Mismatch Sensitivity.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

Optimizing the efficiency of DC-DC converters with an analog variable-frequency controller.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Advancing Data Weighted Averaging Technique for Multi-Bit Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

2006
An automatic coefficient design methodology for high-order bandpass sigma-delta modulator with single-stage structure.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Nyquist-Rate Current-Steering Digital-to-Analog Converters With Random Multiple Data-Weighted Averaging Technique and Q<sup>N</sup> Rotated Walk Switching Scheme.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Design Method for High-Order Sigma-Delta Modulator Stabilized by Departure Angles Designed to Keep Root Loci in Unit Circle.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Current-Mode Converters with Adjustable-Slope Compensating Ramp.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2004
The design of high-order bandpass sigma-delta modulators using low-spread single-stage structure.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

2003
High-speed DACs with random multiple data-weighted averaging algorithm.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
A wideband CMOS sigma-delta modulator with incremental data weighted averaging.
IEEE J. Solid State Circuits, 2002

1993
Multiple-Valued Counter.
IEEE Trans. Computers, 1993


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