Takahide Ikeda

According to our database, Takahide Ikeda authored at least 5 papers between 1989 and 1995.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1995

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM.

Hiroalu Nambu, Kazuo Kanetani, Youji Idei, Tom Masuda, Keiichi Higeta, Masayuki Ohayashi, Masami Usami, Kunihiko Yamaguchi, Toshiyuki Kikuchi, Takahide Ikeda, Kenichi Ohhata, Takeshi Kusunoki, Noriyuki Homma

IEEE J. Solid State Circuits, April, 1995

1994

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates.

Nobuo Tamba, Akio Anzai, Kazuhiro Akimoto, Masayuki Ohayashi, Toshiro Hiramoto, Tadanori Kokubu, Sohei Ohmori, Tetsuya Muraya, Atsuyuki Kishimoto, Sousuke Tsuji, Hideki Hayashi, Nadateru Handa, Toshio Igarashi, Hiroaki Nambu, Makoto Yoshida, Tsuyoshi Fujiwara, Kunihiko Watanabe, Akihisa Uchida, Masanori Odaka, Kunihiko Yamaguchi, Takahide Ikeda

IEEE J. Solid State Circuits, November, 1994

1992

High-speed sensing techniques for ultrahigh-speed SRAMs.

Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Noriyuki Homma, Kunihiko Yamaguchi, Toshiro Hiramoto, Nobuo Tamba, Masanori Odaka, Kunihiko Watanabe, Takahide Ikeda, Kenichi Ohhata, Yoshiaki Sakurai

IEEE J. Solid State Circuits, April, 1992

A 1.5-ns access time, 78- mu m² memory-cell size, 64-kb ECL-CMOS SRAM.

Kunihiko Yamaguchi, Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Noriyuki Homma, Toshiro Hiramoto, Nobuo Tamba, Kunihiko Watanabe, Masanori Odaka, Takahide Ikeda, Kenichi Ohhata, Yoshiaki Sakurai

IEEE J. Solid State Circuits, February, 1992

1989

An 8 ns 256 K BiCMOS RAM.

Nobuo Tamba, Shuuichi Miyaoka, Masanori Odaka, Katsumi Ogiue, Kouichirou Yamada, Takahide Ikeda, Mitsuru Hirao, Hisayuki Higuchi, Hideaki Uchida

IEEE J. Solid State Circuits, August, 1989