Toshiro Hiramoto

According to our database, Toshiro Hiramoto authored at least 29 papers between 1994 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-off Operation, High Mobility and Reliability for 3D Integrated Devices.

Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

3-Layer stacked pixel-parallel CMOS image sensors using hybrid bonding of SOI wafers.

Masahide Goto, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

Proceedings of the Imaging Sensors and Systems 2022, online, January 15-26, 2022, 2022

2021

Recent Progress of Double/Dual-Gate Silicon IGBT Technologies.

Toshiro Hiramoto, Takuya Saraya

Proceedings of the 14th IEEE International Conference on ASIC, 2021

2020

An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing.

Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi, Kiyoshi Takeuchi, Toshiro Hiramoto, Shoichi Iwai, Masami Murakata, Masahiko Yoshimoto

Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020

2019

Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory Based on Non-equilibrium Green Function Method.

Fei Mo, Yusaku Tagawa, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi

Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019

Comprehensive Understanding of Negative Capacitance FET From the Perspective of Transient Ferroelectric Model.

Masaharu Kobayashi, Chengji Jin, Toshiro Hiramoto

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Switching of 3300V Scaled IGBT by 5V Gate Drive.

Toshiro Hiramoto, Katsumi Satoh, Tomoko Matsudai, Wataru Saito, Kuniyuki Kakushima, Takuya Hoshii, Kazuyoshi Furukawa, Masahiro Watanabe, Naoyuki Shigyo, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Atsushi Ogura, Shinichi Nishizawa, Ichiro Omura, Hiromichi Ohashi, Kazuo Itou, Toshihiro Takakura, Munetoshi Fukui, Shinichi Suzuki, Ken Takeuchi, Masanori Tsukuda, Yohichiroh Numasawa

Proceedings of the 13th IEEE International Conference on ASIC, 2019

Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers.

Masahide Goto, Joeri De Vos, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Eiji Higurashi, Yuki Honda, Takuya Saraya, Masaharu Kobayashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018

New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment.

Kuniyuki Kakushima, Takuya Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, Ken Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Y. Numasawa, Atsushi Ogura, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, H. Ohashi, Hiroshi Iwai

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Quarter Video Graphics Array Full-Digital Image Sensing with Wide Dynamic Range and Linear Output Using Pixel-Wise 3D Integration.

Masahide Goto, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately.

Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima, Masahiro Watanabe, Naoyuki Shigvo, Takuya Saraya, Toshihiko Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Lwai

Proceedings of the 48th European Solid-State Device Research Conference, 2018

2017

3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat).

Kazuo Tsutsui, Kuniyuki Kakushima, Takuya Hoshii, A. Nakajima, Shinichi Nishizawa, Hitoshi Wakabayashi, Iriya Muneta, K. Sato, Tomoko Matsudai, Wataru Saito, Takuya Saraya, K. Itou, M. Fukui, S. Suzuki, Masaharu Kobayashi, T. Takakura, Toshiro Hiramoto, Atsushi Ogura, Y. Numasawa, Ichiro Omura, H. Ohashi, Hiroshi Iwai

Proceedings of the 12th IEEE International Conference on ASIC, 2017

Parallel nonvolatile programming of power-up states of SRAM cells.

Toshiro Hiramoto, Tomoko Mizutani, Kiyoshi Takeuchi, Masaharu Kobayashi

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2015

Nanoelectronics Research Gaps and Recommendations: A Report from the International Planning Working Group on Nanoelectronics (IPWGN) [Commentary].

Kosmas Galatsis, Paolo Gargini, Toshiro Hiramoto, Dirk Beernaert, Roger DeKeersmaecker, Joachim Pelka, Lothar Pfitzner

IEEE Technol. Soc. Mag., 2015

Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers.

Masahide Goto, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi, Hiroshi Toshiyoshi, Toshiro Hiramoto

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2013

Statistical Analysis of Current Onset Voltage (COV) Distribution of Scaled MOSFETs.

Tomoko Mizutani, Anil Kumar, Toshiro Hiramoto

IEICE Trans. Electron., 2013

Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress.

Toshiro Hiramoto, Anil Kumar, Takuya Saraya, Shinji Miyano

IEICE Trans. Electron., 2013

NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM.

Nurul Ezaila Alias, Anil Kumar, Takuya Saraya, Shinji Miyano, Toshiro Hiramoto

IEICE Trans. Electron., 2013

2011

Ultra-low-voltage operation: device perspective.

Toshiro Hiramoto

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs.

Toshiro Hiramoto, Anil Kumar, Tomoko Mizutani, Jun Nishimura, Takuya Saraya

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps.

Michel Brillouët, George Bourianoff, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida

Proc. IEEE, 2010

Nanoelectronics Research for Beyond CMOS Information Processing.

George Bourianoff, Michel Brillouët, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida

Proc. IEEE, 2010

2007

Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations.

Toshiro Hiramoto, Toshiharu Nagumo, Tetsu Ohtou, Kouki Yokoyama

IEICE Trans. Electron., 2007

2006

Emerging nanoscale silicon devices taking advantage of nanostructure physics.

Toshiro Hiramoto, Masumi Saitoh, Gen Tsutsui

IBM J. Res. Dev., 2006

2003

VTCMOS characteristics and its optimum conditions predicted by a compact analytical model.

Hyunsik Im, Takashi Inukai, Hiroyuki Gomyo, Toshiro Hiramoto, Takayasu Sakurai

IEEE Trans. Very Large Scale Integr. Syst., 2003

2001

Variable threshold CMOS (VTCMOS) in series connected circuits.

Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000

Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration.

Takashi Inukai, Makoto Takamiya, Kouichi Nose, Hiroshi Kawaguchi, Toshiro Hiramoto, Takayasu Sakurai

Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1994

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates.

Nobuo Tamba, Akio Anzai, Kazuhiro Akimoto, Masayuki Ohayashi, Toshiro Hiramoto, Tadanori Kokubu, Sohei Ohmori, Tetsuya Muraya, Atsuyuki Kishimoto, Sousuke Tsuji, Hideki Hayashi, Nadateru Handa, Toshio Igarashi, Hiroaki Nambu, Makoto Yoshida, Tsuyoshi Fujiwara, Kunihiko Watanabe, Akihisa Uchida, Masanori Odaka, Kunihiko Yamaguchi, Takahide Ikeda

IEEE J. Solid State Circuits, November, 1994

A 1.5-ns cycle-time 18-kb pseudo-dual-port RAM with 9K logic gates.

Masato Iwabuchi, Masami Usami, Masamori Kashiyama, Takashi Oomori, Shigeharu Murata, Toshiro Hiramoto, Takashi Hashimoto, Yasuhiro Nakajima

IEEE J. Solid State Circuits, April, 1994