Takao Oshita

According to our database, Takao Oshita authored at least 4 papers between 2015 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors.

Takao Oshita, Jonathan Douglas, Arun Krishnamoorthy

IEEE Trans. Very Large Scale Integr. Syst., 2019

2016

A Compact First-Order ΣΔ Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process.

Takao Oshita, Joseph Shor, David E. Duarte, Avner Kornfeld, George L. Geannopoulos, Jonathan Douglas, Nasser A. Kurd

IEEE J. Solid State Circuits, 2016

2015

Compact BJT-Based Thermal Sensor for Processor Applications in a 14 nm tri-Gate CMOS Process.

Takao Oshita, Joseph Shor, David E. Duarte, Avner Kornfeld, Dror Zilberman

IEEE J. Solid State Circuits, 2015

Low power analog circuit techniques in the 5^th generation intel core^TM microprocessor (broadwell).

Praveen Mosalikanti, Nasser A. Kurd, Christopher Mozak, Takao Oshita

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015