Takayuki Onishi

According to our database, Takayuki Onishi authored at least 24 papers between 2003 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A Low-Latency 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control for Live Streaming.

Daisuke Kobayashi, Ken Nakamura, Masaki Kitahara, Tatsuya Osawa, Yuya Omori, Takayuki Onishi, Hiroe Iwasaki

IEICE Trans. Inf. Syst., 2023

2020

Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture.

Ken Nakamura, Daisuke Kobayashi, Yuya Omori, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki

IEICE Trans. Electron., 2020

2019

A Low Power Motion Estimation Engine with Adaptive Bit-Shifted SAD Calculation.

Takayuki Onishi, Yuya Omori, Ken Nakamura, Hiroe Iwasaki, Atsushi Shimizu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

An MMT Module for 4K/120fps Temporally Scalable Video.

Yasuhiro Mochida, Takayuki Nakachi, Takahiro Yamaguchi, Takayuki Onishi, Ken Nakamura

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Image Pre-Transformation for Recognition-Aware Image Compression.

Satoshi Suzuki, Motohiro Takagi, Kazuya Hayase, Takayuki Onishi, Atsushi Shimizu

Proceedings of the 2019 IEEE International Conference on Image Processing, 2019

4K 120fps HEVC Temporal Scalable Encoder with Super Low Delay.

Yuya Omori, Ken Nakamura, Takayuki Onishi, Daisuke Kobayashi, Tatsuya Osawa, Hiroe Iwasaki

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A Real-Time 4K HEVC Multi-Channel Encoding System with Content-Aware Bitrate Control.

Daisuke Kobayashi, Ken Nakamura, Tatsuya Osawa, Yuya Omori, Takayuki Onishi, Hiroe Iwasaki

Proceedings of the 2019 IEEE Global Communications Conference, 2019

Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture.

Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki, Atsushi Shimizu

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2019

2018

A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K.

Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu

IEEE Trans. Very Large Scale Integr. Syst., 2018

A 120 fps High Frame Rate Real-time HEVC Video Encoder with Parallel Configuration Scalable to 4K.

Yuya Omori, Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu

IEEE Trans. Multi Scale Comput. Syst., 2018

A 4K/60p HEVC Real-Time Encoding System With High Quality HDR Color Representations.

Daisuke Kobayashi, Ken Nakamura, Takayuki Onishi, Hiroe Iwasaki, Atsushi Shimizu

IEEE Trans. Consumer Electron., 2018

An HEVC real-time encoding system with high quality HDR color representations.

Daisuke Kobayashi, Ken Nakamura, Takayuki Onishi, Yasuyuki Nakajima, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu

Proceedings of the IEEE International Conference on Consumer Electronics, 2018

2015

Single-chip 4K 60fps 4: 2: 2 HEVC video encoder LSI with 8K scalability.

Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu

Proceedings of the Symposium on VLSI Circuits, 2015

Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure.

Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura, Koyo Nitta, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Mitsuo Ikeda, Atsushi Shimizu

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2012

An H.264/AVC High422 Profile and MPEG-2 422 Profile Encoder LSI for HDTV Broadcasting Infrastructures.

Koyo Nitta, Hiroe Iwasaki, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Yasuyuki Nakajima, Minoru Inamori, Ryuichi Tanida, Atsushi Shimizu, Ken Nakamura, Mitsuo Ikeda, Jiro Naganuma

IEICE Trans. Electron., 2012

MVC real-time video encoder for full-HDTV 3D video.

Mitsuo Ikeda, Takayuki Onishi, Takashi Sano, Atsushi Sagata, Hiroe Iwasaki, Yasuyuki Nakajima, Koyo Nitta, Yasuko Takahashi, Kazuya Yokohari, Daisuke Kobayashi, Kazuto Kamikura, Hirohisa Jozawa

Proceedings of the IEEE International Conference on Consumer Electronics, 2012

2008

A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV.

Takayuki Onishi, Ken Nakamura, Takeshi Yoshitome, Jiro Naganuma

IEICE Trans. Inf. Syst., 2008

Multi-reference and multi-block-size motion estimation with flexible mode selection for professional 4: 2: 2 H.264/AVC encoder LSI.

Takayuki Onishi, Takashi Sano, Koyo Nitta, Mitsuo Ikeda, Jiro Naganuma

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level.

Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Toshihiro Minami, Makoto Endo, Yoshiyuki Yashima

IEEE Trans. Very Large Scale Integr. Syst., 2007

2006

Highly accurate de-jittering scheme for broadcast quality video transmission.

Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima

Syst. Comput. Jpn., 2006

2005

New set-top box for interactive visual communication of home entertainment using MPEG-2 full-duplex CODEC LSI.

Minoru Inamori, Hiroe Iwasaki, Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Yoshiyuki Yashima

IEEE Trans. Consumer Electron., 2005

2004

A distributed TS-MUX architecture for multi-chip extension beyond the HDTV level.

Takayuki Onishi, Mitsuo Ikeda, Jiro Naganuma, Makoto Endo, Yoshiyuki Yashima

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level.

Hiroe Iwasaki, Jiro Naganuma, Koyo Nitta, Ken Nakamura, Takeshi Yoshitome, Mitsuo Ogura, Yasuyuki Nakajima, Yutaka Tashiro, Takayuki Onishi, Mitsuo Ikeda, Makoto Endo

Proceedings of the 2003 Design, 2003

A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems.

Hiroe Iwasaki, Jiro Naganuma, Yasuyuki Nakajima, Yutaka Tashiro, Ken Nakamura, Takeshi Yoshitome, Takayuki Onishi, Mitsuo Ikeda, Takaaki Izuoka, Makoto Endo

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003