Tero Sihvo

According to our database1, Tero Sihvo authored at least 3 papers between 2000 and 2004.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2004
Byte and modulo addressable parallel memory architecture for video coding.
IEEE Trans. Circuits Syst. Video Technol., 2004

2000
Parallel, memory access schemes for H.263 encoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Verifying external data memory interface for H.263 video DSP with memory simulator.
Proceedings of the 10th European Signal Processing Conference, 2000


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