Jarmo Takala

Proceedings of the Handbook of Hardware/Software Codesign., 2017

MergeTree: A Fast Hardware HLBVH Constructor for Animated Ray Tracing.

[BibT_eX]

[DOI]

ACM Trans. Graph., 2017

Hardware design methodology using lightweight dataflow and its integration with low power techniques.

[BibT_eX]

[DOI]

J. Syst. Archit., 2017

Fast Hardware Construction and Refitting of Quantized Bounding Volume Hierarchies.

[BibT_eX]

[DOI]

Comput. Graph. Forum, 2017

Multiplierless reconfigurable processing element for mixed radix-2/3/4/5 FFTs.

[BibT_eX]

[DOI]

Muazam Ali

Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Foveated instant preview for progressive rendering.

[BibT_eX]

[DOI]

Proceedings of the SIGGRAPH Asia 2017 Technical Briefs, Bangkok, Thailand, November 27, 2017

Exposed datapath optimizations for loop scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Design and implementation of a multi-mode harris corner detector architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Multiplierless unified architecture for mixed radix-2/3/4 FFTs.

[BibT_eX]

[DOI]

Proceedings of the 25th European Signal Processing Conference, 2017

Twiddle factor complexity analysis of Radix-2 FFT algorithms for pipelined architectures.

[BibT_eX]

[DOI]

Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016

Improving Code Density with Variable Length Encoding Aware Instruction Scheduling.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2016

IEEE 802.11ac MIMO Transceiver Baseband Processing on a VLIW Processor.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2016

Integer Linear Programming-Based Scheduling for Transport Triggered Architectures.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2016

Robust Misalignment Handling in Pedestrian Dead Reckoning.

[BibT_eX]

[DOI]

Proceedings of the IEEE 84th Vehicular Technology Conference, 2016

Real-time implementation of dice unloading algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

New Identical Radix-2^k Fast Fourier Transform Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Hardware-Efficient Twiddle Factor Generator for Mixed Radix-2/3/4/5 FFTs.

[BibT_eX]

[DOI]

Tomasz Patyk

Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Multi bounding volume hierarchies for ray tracing pipelines.

[BibT_eX]

[DOI]

Proceedings of the SIGGRAPH ASIA 2016, Macao, December 5-8, 2016 - Technical Briefs, 2016

Hardware-efficient index mapping for mixed radix-2/3/4/5 FFTs.

[BibT_eX]

[DOI]

Tomasz Patyk

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Aggressively bypassing list scheduler for transport triggered architectures.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

OpenCL programmable exposed datapath high performance low-power image signal processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Foveated Path Tracing - A Literature Review and a Performance Gain Analysis.

[BibT_eX]

[DOI]

Proceedings of the Advances in Visual Computing - 12th International Symposium, 2016

Customized high performance low power processor for binaural speaker localization.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Half-precision Floating-point Ray Traversal.

[BibT_eX]

[DOI]

Proceedings of the 11th Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications (VISIGRAPP 2016), 2016

Software defined radio implementation of adaptive nonlinear digital self-interference cancellation for mobile inband full-duplex radio.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Global Conference on Signal and Information Processing, 2016

Resource-constrained implementation and optimization of a deep neural network for vehicle classification.

[BibT_eX]

[DOI]

Renjie Xie

Heikki Huttunen

Shuoxin Lin

Proceedings of the 24th European Signal Processing Conference, 2016

Low power design methodology for signal processing systems using lightweight dataflow techniques.

[BibT_eX]

[DOI]

Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2015

Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2015

Code Density and Energy Efficiency of Exposed Datapath Architectures.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2015

Effect of Carouseling on Angular Rate Sensor Error Processes.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2015

pocl: A Performance-Portable OpenCL Implementation.

[BibT_eX]

[DOI]

Carlos Sánchez de La Lama

Int. J. Parallel Program., 2015

MergeTree: a HLBVH constructor for mobile systems.

[BibT_eX]

[DOI]

Proceedings of the SIGGRAPH Asia 2015 Technical Briefs, Kobe, Japan, November 2-6, 2015, 2015

Power optimizations for transport triggered SIMD processors.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Pedestrian localization in moving platforms using dead reckoning, particle filtering and map matching.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

Rapid customization of image processors using Halide.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Global Conference on Signal and Information Processing, 2015

HSA-enabled DSPs and accelerators.

[BibT_eX]

[DOI]

John Glossner

Paul Blinzer

Proceedings of the 2015 IEEE Global Conference on Signal and Information Processing, 2015

Parallel processing intensive digital front-end for IEEE 802.11ac receiver.

[BibT_eX]

[DOI]

Mona Aghababaee Tafreshi

Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014

Indoor Localization Methods Using Dead Reckoning and 3D Map Matching.

[BibT_eX]

[DOI]

Jayaprasad Bojja

J. Signal Process. Syst., 2014

Distributed Indoor Positioning System With Inertial Measurements and Map Matching.

[BibT_eX]

[DOI]

Arto Perttula

Helena Leppäkoski

Pavel Davidson

IEEE Trans. Instrum. Meas., 2014

Compiler optimizations for code density of variable length instructions.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

IEEE 802.11ac MIMO receiver baseband processing on customized VLIW processor.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Automatic crash detection for motor cycles.

[BibT_eX]

[DOI]

Proceedings of the IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, Dallas, TX, USA, October 29, 2014

Efficient software synthesis of dynamic dataflow programs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2014

Efficient architecture mapping of FFT/IFFT for cognitive radio networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2014

IEEE 802.11AC MIMO transmitter baseband processing on customized VLIW processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2014

Heuristics for greedy transport triggered architecture interconnect exploration.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Compilers, 2014

2013

General-Purpose DSP Processors.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Signal Processing Systems, 2013

Guest Editors' Introduction to Special Issue on Advances in DSP System Design.

[BibT_eX]

[DOI]

Warren J. Gross

Wonyong Sung

J. Signal Process. Syst., 2013

Pedestrian Navigation Based on Inertial Sensors, Indoor Map, and WLAN Signals.

[BibT_eX]

[DOI]

Helena Leppäkoski

J. Signal Process. Syst., 2013

Use of compiler optimization of software bypassing as a method to improve energy efficiency of exposed data path architectures.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2013

Using Building Plans and Self-Contained Sensors with GNSS Initialization for Indoor Navigation.

[BibT_eX]

[DOI]

Proceedings of the 77th IEEE Vehicular Technology Conference, 2013

Inexpensive correctly rounded floating-point division and square root with input scaling.

[BibT_eX]

[DOI]

Timo Viitanen

Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Systematic method to convert of analog filters to digital filters.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Low-power application-specific FFT processor for LTE applications.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Turbo decoding on tailored OpenCL processor.

[BibT_eX]

[DOI]

Proceedings of the 2013 9th International Wireless Communications and Mobile Computing Conference, 2013

Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013

Method to convert analog filters to digital filters.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013

Energy consumption analysis for green routing - Data collection from electric vehicles.

[BibT_eX]

[DOI]

Proceedings of the IECON 2013, 2013

Simplified floating-point division and square root.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2013

Indoor 3D navigation and positioning of vehicles in multi-storey parking garages.

[BibT_eX]

[DOI]

Jayaprasad Bojja

Proceedings of the IEEE International Conference on Acoustics, 2013

Pipelined FFT for wireless communications supporting 128-2048 / 1536 -point transforms.

[BibT_eX]

[DOI]

Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013

2012

Guest Editors' Introduction.

[BibT_eX]

[DOI]

Wonyong Sung

J. Signal Process. Syst., 2012

Zero-Quantized Inter DCT Coefficient Prediction for Real-Time Video Coding.

[BibT_eX]

[DOI]

Jin Li

Moncef Gabbouj

IEEE Trans. Circuits Syst. Video Technol., 2012

Improving TTFF by Two-Satellite GNSS Positioning.

[BibT_eX]

[DOI]

Jussi Parviainen

IEEE Trans. Aerosp. Electron. Syst., 2012

Circulant Hermitian Matrix Inversion Method Based on Discrete Cosine and Sine Transforms.

[BibT_eX]

[DOI]

David Guevorkian

Kim Rounioja

Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Irreversibility induced density limits and logical reversiblity in nanocircuits.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

2011

Low-Power Application-Specific Processor for FFT Computations.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2011

Design Methodology for Offloading Software Executions to FPGA.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2011

Coding method for embedding audio in video stream.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

TCEMC: A co-design flow for application-specific multicores.

[BibT_eX]

[DOI]

José Ignacio Martínez

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Instruction buffer with limited control flow and loop nest support.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Customizable Datapath Integrated Lock Unit.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on System on Chip, 2011

Effects of loop unrolling and use of instruction buffer on processor energy consumption.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Symposium on System on Chip, 2011

Irreversible bit erasures in binary multipliers.

[BibT_eX]

[DOI]

Craig S. Lent

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Conflict-free parallel access scheme for mixed-radix FFT supporting I/O permutations.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2011

Prediction of discrete cosine transformed coefficients in resized pixel blocks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2011

Lossless audio hiding method for synchronous audio-video coding.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2011

Operation set customization in retargetable compilers.

[BibT_eX]

[DOI]

Heikki Kultala

Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010

Binary Adders on Quantum-Dot Cellular Automata.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2010

Optimizing radio map for WLAN fingerprinting.

[BibT_eX]

[DOI]

Helena Leppäkoski

Saija Tikkinen

Proceedings of the Ubiquitous Positioning Indoor Navigation and Location Based Service, 2010

Application of particle filters for indoor positioning using floor plans.

[BibT_eX]

[DOI]

Pavel Davidson

Proceedings of the Ubiquitous Positioning Indoor Navigation and Location Based Service, 2010

OpenCL-based design methodology for application-specific processors.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Reducing instruction memory energy consumption by using Instruction Buffer and after scheduling analysis.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Customized Exposed Datapath Soft-Core Design Flow with Compiler Support.

[BibT_eX]

[DOI]

José Ignacio Martínez

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

General-Purpose DSP Processors.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Signal Processing Systems, 2010

2009

Parallel Memory Architecture for Application-Specific Instruction-Set Processors.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

Dictionary-based program compression on customizable processor architectures.

[BibT_eX]

[DOI]

Jari Heikkinen

Henk Corporaal

Microprocess. Microsystems, 2009

3G Long Term Evolution Baseband Processing with Application-Specific Processors.

[BibT_eX]

[DOI]

Int. J. Digit. Multim. Broadcast., 2009

Reconfigurable video decoder with transform acceleration.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Reducing processor energy consumption by compiler optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Programmable and Scalable Architecture for Graphics Processing Units.

[BibT_eX]

[DOI]

Carlos S. de La Lama

Proceedings of the Embedded Computer Systems: Architectures, 2009

Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2009

Merged inverse quantization and IDCT for optimized decoder implementation.

[BibT_eX]

[DOI]

Proceedings of the 17th European Signal Processing Conference, 2009

SPICE Simulation of Analog Filters: A Method for Designing Digital Filters.

[BibT_eX]

[DOI]

Corneliu Rusu

Lacrimioara Grama

Proceedings of the Computer Aided Systems Theory, 2009

2008

Introduction to the Special Issue on Embedded Computing Systems for DSP.

[BibT_eX]

[DOI]

Georgi Gaydadjiev

J. Signal Process. Syst., 2008

A Programmable Max-Log-MAP Turbo Decoder Implementation.

[BibT_eX]

[DOI]

VLSI Design, 2008

Hybrid Modeling of Intra-DCT Coefficients for Real-Time Video Encoding.

[BibT_eX]

[DOI]

Jin Li

Moncef Gabbouj

EURASIP J. Image Video Process., 2008

Low-complexity polynomials modulo integer with linearly incremented variable.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2008

Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2008

Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2008

Fine-grained application-specific instruction set processor design for the K-best list sphere detector algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Reliability of n-Bit Nanotechnology Adder.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Trade-offs in mapping high-level dataflow graphs onto ASIPs.

[BibT_eX]

[DOI]

Pertti Kellomäki

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Laplacian modeling of DCT coefficients for real-time encoding.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

Low-power signal acquisition for galileo satellite navigation system.

[BibT_eX]

[DOI]

Tero Partanen

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Complex-valued QR decomposition implementation for MIMO receivers.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2008

A detection algorithm for zero-quantized DCT coefficients in JPEG.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2008

Implementing communications systems on an SDR SoC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2008

Reducing Context Switch Overhead with Compiler-Assisted Threading.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

2007

Dual Antenna Receivers for High Data Rate Terminals.

[BibT_eX]

[DOI]

Wirel. Pers. Commun., 2007

Stride Permutation Networks for Array Processors.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2007

Editorial.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

Effects of program compression.

[BibT_eX]

[DOI]

Jari Heikkinen

J. Syst. Archit., 2007

Embedded Digital Signal Processing Systems.

[BibT_eX]

[DOI]

Gang Qu

EURASIP J. Embed. Syst., 2007

Application-Specific Instruction Set Processor Implementation of List Sphere Detector.

[BibT_eX]

[DOI]

EURASIP J. Embed. Syst., 2007

Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations.

[BibT_eX]

[DOI]

Chung-Ching Shen

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Memory-Based List Updating for List Sphere Decoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Parallel Memory Architecture for TTA Processor.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2007

Low-Power Twiddle Factor Unit for FFT Computation.

[BibT_eX]

[DOI]

Tero Partanen

Proceedings of the Embedded Computer Systems: Architectures, 2007

Resource Conflict Detection in Simulation of Function Unit Pipelines.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2007

Efficient parallel memory organization for turbo decoders.

[BibT_eX]

[DOI]

Ruirui Gu

Proceedings of the 15th European Signal Processing Conference, 2007

Pipelined array multiplier based on quantum-dot cellular automata.

[BibT_eX]

[DOI]

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

Robust Adders Based on Quantum-Dot Cellular Automata.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006

Scalable FFT Processors and Pipelined Butterfly Units.

[BibT_eX]

[DOI]

Konsta Punkka

J. VLSI Signal Process., 2006

Discrete cosine and sine transforms - regular algorithms and pipeline architectures.

[BibT_eX]

[DOI]

Jari Nikara

Jaakko Astola

Signal Process., 2006

Software Pipelining Support for Transport Triggered Architecture Processors.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2006

Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2006

Software Implementation of WiMAX on the Sandbridge SandBlaster Platform.

[BibT_eX]

[DOI]

Daniel Iancu

Hua Ye

Emanoil Surducan

Murugappan Senthilvelan

Proceedings of the Embedded Computer Systems: Architectures, 2006

[BibT_eX]

[DOI]

Chung-Ching Shen

Proceedings of the International Symposium on System-on-Chip, 2006

Loop Scheduling for Transport Triggered Architecture Processors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on System-on-Chip, 2006

Analog Television, WiMAX and DVB-H on the Same SoC Platform.

[BibT_eX]

[DOI]

Daniel Iancu

Hua Ye

Vladimir Kotlyar

Murugappan Senthilvelan

Proceedings of the International Symposium on System-on-Chip, 2006

Programmability in Dictionary-Based Compression.

[BibT_eX]

[DOI]

Jari Heikkinen

Proceedings of the International Symposium on System-on-Chip, 2006

Evaluation of stride permutation networks.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Systematic approach for path metric access in Viterbi decoders.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 2005

Hardware Cost Estimation for Application-Specific Processor Design.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2005

Dictionary-based program compression on transport triggered architectures.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Efficient byte permutation realizations for compact AES implementations.

[BibT_eX]

[DOI]

Proceedings of the 13th European Signal Processing Conference, 2005

256-State Rate 1/2 Viterbi Decoder on TTA Processor.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Complex Fixed-Point Matrix Inversion Using Transport Triggered Architecture.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004

Multiple-symbol parallel decoding for variable length codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

[BibT_eX]

[DOI]

Tuomas Järvinen

Proceedings of the Computer Systems: Architectures, 2004

Direct versus iterative methods for fixed-point implementation of matrix inversion.

[BibT_eX]

[DOI]

Mikko Ylinen

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A low-power fractional decimator architecture for an IF-sampling dual-mode receiver.

[BibT_eX]

[DOI]

Riku Uusikartano

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

VLSI-efficient implementation of full adder-based median filter.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Roles of pulse position modulation on intrachannel nonlinearities affected high-bit-rate optic fiber channel.

[BibT_eX]

[DOI]

Sun Linghao

Proceedings of IEEE International Conference on Communications, 2004

Implementation of two-dimensional discrete cosine transform and its inverse.

[BibT_eX]

[DOI]

Proceedings of the 2004 12th European Signal Processing Conference, 2004

Evolved gate arrays for image restoration.

[BibT_eX]

[DOI]

Proceedings of the IEEE Congress on Evolutionary Computation, 2004

2003

Multistage interconnection networks for parallel Viterbi decoders.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 2003

FPGA-Based Variable Length Decoders.

[BibT_eX]

Proceedings of the IFIP VLSI-SoC 2003, 2003

In-Place Storage of Path Metrics in Viterbi Decoders.

[BibT_eX]

Proceedings of the IFIP VLSI-SoC 2003, 2003

Parallel memory access in turbo decoders.

[BibT_eX]

[DOI]

Proceedings of the IEEE 14th International Symposium on Personal, 2003

On allocation of turbo decoder iterations.

[BibT_eX]

[DOI]

Proceedings of the IEEE 14th International Symposium on Personal, 2003

Mapping Action Systems to Hardware Descriptions.

[BibT_eX]

Jussi Nykänen

Harri Klapuri

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Evaluating Template-Based Instruction Compression on Transport Triggered Architectures.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Updating matrix inverse in fixed-point representation: direct versus iterative methods.

[BibT_eX]

[DOI]

Mikko Ylinen

Proceedings of the 2003 International Symposium on System-on-Chip, 2003

Immediate optimization for compressed transport triggered architecture instructions.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on System-on-Chip, 2003

Conflict-free parallel memory access scheme for FFT processors.

[BibT_eX]

[DOI]

Tuomas Järvinen

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Parallel iterations for recursive median filter.

[BibT_eX]

[DOI]

Marina Dana Topa

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A recurrent neural network for 1-D phase retrieval.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

[BibT_eX]

[DOI]

Tuomas Järvinen

Jari Nikara

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Pipeline architecture for two-dimensional discrete cosine transform and its inverse.

[BibT_eX]

[DOI]

Jari Nikara

Konsta Punkka

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Parallel Multiple-Symbol Variable-Length Decoding.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001

Implementing reactive closed-system specifications.

[BibT_eX]

[DOI]

Harri Klapuri

Jukka Saarinen

J. Netw. Comput. Appl., 2001

Pipeline architecture for DCT/IDCT.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Multi-port interconnection networks for radix-R algorithms.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2001

2000

Constant geometry algorithm for discrete cosine transform.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2000

Parallel, memory access schemes for H.263 encoder.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Scalable interconnection networks for partial column array processor architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Pipeline architecture for 8×8 discrete cosine transform.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2000

Pipelined architecture for inverse discrete cosine transform.

[BibT_eX]

[DOI]

Proceedings of the 10th European Signal Processing Conference, 2000

1999

Safety, liveness and real-time in embedded system design.

[BibT_eX]

[DOI]

Harri Klapuri

Jukka Saarinen

J. Netw. Comput. Appl., 1999

Distance Transform Algorithm for Bit-Serial SIMD Architectures.

[BibT_eX]

[DOI]

Jouko O. Viitanen

Comput. Vis. Image Underst., 1999

Hardware architecture for real-time distance transform.

[BibT_eX]

[DOI]

Jouko O. Viitanen

Jukka Saarinen

Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

1994

SIMD Parallel Calculation of Distance Transformations.

[BibT_eX]

[DOI]

Jouko O. Viitanen