Jarmo Takala

According to our database1, Jarmo Takala authored at least 189 papers between 1988 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Exploiting Task Parallelism with OpenCL: A Case Study.
Signal Processing Systems, 2019

LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor.
IEEE Trans. VLSI Syst., 2019

Programmable and Scalable Architecture for Graphics Processing Units.
T. HiPEAC, 2019

An integrated hardware/software design methodology for signal processing systems.
Journal of Systems Architecture - Embedded Systems Design, 2019

Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture.
CoRR, 2019

Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture.
Proceedings of the IEEE International Conference on Acoustics, 2019

2018
Instruction Fetch Energy Reduction with Biased SRAMs.
Signal Processing Systems, 2018

Software Defined Radio Implementation of a Digital Self-interference Cancellation Method for Inband Full-Duplex Radio Using Mobile Processors.
Signal Processing Systems, 2018

PLOCTree: A Fast, High-Quality Hardware BVH Builder.
PACMCGIT, 2018

Variable Length Instruction Compression on Transport Triggered Architectures.
International Journal of Parallel Programming, 2018

Instantaneous foveated preview for progressive Monte Carlo rendering.
Computational Visual Media, 2018

LoTTA: Energy-Efficient Processor for Always-On Applications.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

AivoTTA: an energy efficient programmable accelerator for CNN-based object recognition.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Transport-Triggered Soft Cores.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

Sparse Sampling for Real-time Ray Tracing.
Proceedings of the 13th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications (VISIGRAPP 2018), 2018

2017
Codesign Case Study on Transport-Triggered Architectures.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

MergeTree: A Fast Hardware HLBVH Constructor for Animated Ray Tracing.
ACM Trans. Graph., 2017

Hardware design methodology using lightweight dataflow and its integration with low power techniques.
Journal of Systems Architecture - Embedded Systems Design, 2017

Fast Hardware Construction and Refitting of Quantized Bounding Volume Hierarchies.
Comput. Graph. Forum, 2017

Multiplierless reconfigurable processing element for mixed radix-2/3/4/5 FFTs.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Foveated instant preview for progressive rendering.
Proceedings of the SIGGRAPH Asia 2017 Technical Briefs, Bangkok, Thailand, November 27, 2017

Exposed datapath optimizations for loop scheduling.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Design and implementation of a multi-mode harris corner detector architecture.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017

Multiplierless unified architecture for mixed radix-2/3/4 FFTs.
Proceedings of the 25th European Signal Processing Conference, 2017

Twiddle factor complexity analysis of Radix-2 FFT algorithms for pipelined architectures.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
Improving Code Density with Variable Length Encoding Aware Instruction Scheduling.
Signal Processing Systems, 2016

IEEE 802.11ac MIMO Transceiver Baseband Processing on a VLIW Processor.
Signal Processing Systems, 2016

Integer Linear Programming-Based Scheduling for Transport Triggered Architectures.
TACO, 2016

pocl: A Performance-Portable OpenCL Implementation.
CoRR, 2016

Robust Misalignment Handling in Pedestrian Dead Reckoning.
Proceedings of the IEEE 84th Vehicular Technology Conference, 2016

Real-time implementation of dice unloading algorithm.
Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

New Identical Radix-2^k Fast Fourier Transform Algorithms.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Hardware-Efficient Twiddle Factor Generator for Mixed Radix-2/3/4/5 FFTs.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Multi bounding volume hierarchies for ray tracing pipelines.
Proceedings of the SIGGRAPH ASIA 2016, Macao, December 5-8, 2016 - Technical Briefs, 2016

Hardware-efficient index mapping for mixed radix-2/3/4/5 FFTs.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Aggressively bypassing list scheduler for transport triggered architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

OpenCL programmable exposed datapath high performance low-power image signal processor.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Foveated Path Tracing - A Literature Review and a Performance Gain Analysis.
Proceedings of the Advances in Visual Computing - 12th International Symposium, 2016

Customized high performance low power processor for binaural speaker localization.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Half-precision Floating-point Ray Traversal.
Proceedings of the 11th Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications (VISIGRAPP 2016), 2016

Software defined radio implementation of adaptive nonlinear digital self-interference cancellation for mobile inband full-duplex radio.
Proceedings of the 2016 IEEE Global Conference on Signal and Information Processing, 2016

Resource-constrained implementation and optimization of a deep neural network for vehicle classification.
Proceedings of the 24th European Signal Processing Conference, 2016

Low power design methodology for signal processing systems using lightweight dataflow techniques.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2015
Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs.
Signal Processing Systems, 2015

Code Density and Energy Efficiency of Exposed Datapath Architectures.
Signal Processing Systems, 2015

Effect of Carouseling on Angular Rate Sensor Error Processes.
IEEE Trans. Instrumentation and Measurement, 2015

pocl: A Performance-Portable OpenCL Implementation.
International Journal of Parallel Programming, 2015

MergeTree: a HLBVH constructor for mobile systems.
Proceedings of the SIGGRAPH Asia 2015 Technical Briefs, Kobe, Japan, November 2-6, 2015, 2015

Power optimizations for transport triggered SIMD processors.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Pedestrian localization in moving platforms using dead reckoning, particle filtering and map matching.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

Rapid customization of image processors using Halide.
Proceedings of the 2015 IEEE Global Conference on Signal and Information Processing, 2015

HSA-enabled DSPs and accelerators.
Proceedings of the 2015 IEEE Global Conference on Signal and Information Processing, 2015

Parallel processing intensive digital front-end for IEEE 802.11ac receiver.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
Indoor Localization Methods Using Dead Reckoning and 3D Map Matching.
Signal Processing Systems, 2014

Distributed Indoor Positioning System With Inertial Measurements and Map Matching.
IEEE Trans. Instrumentation and Measurement, 2014

Compiler optimizations for code density of variable length instructions.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

IEEE 802.11ac MIMO receiver baseband processing on customized VLIW processor.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Variable length instruction compression on Transport Triggered Architectures.
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Automatic crash detection for motor cycles.
Proceedings of the IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, Dallas, TX, USA, October 29, 2014

Efficient software synthesis of dynamic dataflow programs.
Proceedings of the IEEE International Conference on Acoustics, 2014

Efficient architecture mapping of FFT/IFFT for cognitive radio networks.
Proceedings of the IEEE International Conference on Acoustics, 2014

IEEE 802.11AC MIMO transmitter baseband processing on customized VLIW processor.
Proceedings of the IEEE International Conference on Acoustics, 2014

Heuristics for greedy transport triggered architecture interconnect exploration.
Proceedings of the 2014 International Conference on Compilers, 2014

2013
Guest Editors' Introduction to Special Issue on Advances in DSP System Design.
Signal Processing Systems, 2013

Pedestrian Navigation Based on Inertial Sensors, Indoor Map, and WLAN Signals.
Signal Processing Systems, 2013

Use of compiler optimization of software bypassing as a method to improve energy efficiency of exposed data path architectures.
EURASIP J. Emb. Sys., 2013

Effect of Carouseling on Angular Rate Sensor Error Processes.
CoRR, 2013

Using Building Plans and Self-Contained Sensors with GNSS Initialization for Indoor Navigation.
Proceedings of the 77th IEEE Vehicular Technology Conference, 2013

Inexpensive correctly rounded floating-point division and square root with input scaling.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Systematic method to convert of analog filters to digital filters.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Low-power application-specific FFT processor for LTE applications.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Turbo decoding on tailored OpenCL processor.
Proceedings of the 2013 9th International Wireless Communications and Mobile Computing Conference, 2013

Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms.
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013

Method to convert analog filters to digital filters.
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013

Simplified floating-point division and square root.
Proceedings of the IEEE International Conference on Acoustics, 2013

Indoor 3D navigation and positioning of vehicles in multi-storey parking garages.
Proceedings of the IEEE International Conference on Acoustics, 2013

Pipelined FFT for wireless communications supporting 128-2048 / 1536 -point transforms.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013

2012
Guest Editors' Introduction.
Signal Processing Systems, 2012

Zero-Quantized Inter DCT Coefficient Prediction for Real-Time Video Coding.
IEEE Trans. Circuits Syst. Video Techn., 2012

Improving TTFF by Two-Satellite GNSS Positioning.
IEEE Trans. Aerospace and Electronic Systems, 2012

Circulant Hermitian Matrix Inversion Method Based on Discrete Cosine and Sine Transforms.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Irreversibility induced density limits and logical reversiblity in nanocircuits.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Pedestrian navigation based on inertial sensors, indoor map, and WLAN signals.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

2011
Low-Power Application-Specific Processor for FFT Computations.
Signal Processing Systems, 2011

Design Methodology for Offloading Software Executions to FPGA.
Signal Processing Systems, 2011

Coding method for embedding audio in video stream.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

TCEMC: A co-design flow for application-specific multicores.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Instruction buffer with limited control flow and loop nest support.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Customizable Datapath Integrated Lock Unit.
Proceedings of the 2011 International Symposium on System on Chip, 2011

Effects of loop unrolling and use of instruction buffer on processor energy consumption.
Proceedings of the 2011 International Symposium on System on Chip, 2011

Irreversible bit erasures in binary multipliers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Conflict-free parallel access scheme for mixed-radix FFT supporting I/O permutations.
Proceedings of the IEEE International Conference on Acoustics, 2011

Prediction of discrete cosine transformed coefficients in resized pixel blocks.
Proceedings of the IEEE International Conference on Acoustics, 2011

Lossless audio hiding method for synchronous audio-video coding.
Proceedings of the IEEE International Conference on Acoustics, 2011

Operation set customization in retargetable compilers.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
Binary Adders on Quantum-Dot Cellular Automata.
Signal Processing Systems, 2010

Optimizing radio map for WLAN fingerprinting.
Proceedings of the Ubiquitous Positioning Indoor Navigation and Location Based Service, 2010

Application of particle filters for indoor positioning using floor plans.
Proceedings of the Ubiquitous Positioning Indoor Navigation and Location Based Service, 2010

OpenCL-based design methodology for application-specific processors.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Customized Exposed Datapath Soft-Core Design Flow with Compiler Support.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

General-Purpose DSP Processors.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
Parallel Memory Architecture for Application-Specific Instruction-Set Processors.
Signal Processing Systems, 2009

Dictionary-based program compression on customizable processor architectures.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

3G Long Term Evolution Baseband Processing with Application-Specific Processors.
Int. J. Digital Multimedia Broadcasting, 2009

Reconfigurable video decoder with transform acceleration.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Reducing processor energy consumption by compiler optimization.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Programmable and Scalable Architecture for Graphics Processing Units.
Proceedings of the Embedded Computer Systems: Architectures, 2009

Radix-4 Recoded Multiplier on Quantum-Dot Cellular Automata.
Proceedings of the Embedded Computer Systems: Architectures, 2009

Low-power application-specific processor for FFT computations.
Proceedings of the IEEE International Conference on Acoustics, 2009

Merged inverse quantization and IDCT for optimized decoder implementation.
Proceedings of the 17th European Signal Processing Conference, 2009

SPICE Simulation of Analog Filters: A Method for Designing Digital Filters.
Proceedings of the Computer Aided Systems Theory, 2009

2008
Introduction to the Special Issue on Embedded Computing Systems for DSP.
Signal Processing Systems, 2008

A Programmable Max-Log-MAP Turbo Decoder Implementation.
VLSI Design, 2008

Hybrid Modeling of Intra-DCT Coefficients for Real-Time Video Encoding.
EURASIP J. Image and Video Processing, 2008

Low-complexity polynomials modulo integer with linearly incremented variable.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Efficient Reed-Solomon Iterative Decoder Using Galois Field Instruction Set.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Arithmetic Design on Quantum-Dot Cellular Automata Nanotechnology.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic.
Proceedings of the Embedded Computer Systems: Architectures, 2008

Fine-grained application-specific instruction set processor design for the K-best list sphere detector algorithm.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Reliability of n-Bit Nanotechnology Adder.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Laplacian modeling of DCT coefficients for real-time encoding.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

Low-power signal acquisition for galileo satellite navigation system.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Complex-valued QR decomposition implementation for MIMO receivers.
Proceedings of the IEEE International Conference on Acoustics, 2008

A detection algorithm for zero-quantized DCT coefficients in JPEG.
Proceedings of the IEEE International Conference on Acoustics, 2008

Implementing communications systems on an SDR SoC.
Proceedings of the IEEE International Conference on Acoustics, 2008

Reducing Context Switch Overhead with Compiler-Assisted Threading.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008

2007
Dual Antenna Receivers for High Data Rate Terminals.
Wireless Personal Communications, 2007

Stride Permutation Networks for Array Processors.
VLSI Signal Processing, 2007

Editorial.
Journal of Systems Architecture, 2007

Effects of program compression.
Journal of Systems Architecture, 2007

Embedded Digital Signal Processing Systems.
EURASIP J. Emb. Sys., 2007

Application-Specific Instruction Set Processor Implementation of List Sphere Detector.
EURASIP J. Emb. Sys., 2007

Synthesis of DSP Architectures Using Libraries of Coarse-Grain Configurations.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Memory-Based List Updating for List Sphere Decoders.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Parallel Memory Architecture for TTA Processor.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Low-Power Twiddle Factor Unit for FFT Computation.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Resource Conflict Detection in Simulation of Function Unit Pipelines.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Efficient parallel memory organization for turbo decoders.
Proceedings of the 15th European Signal Processing Conference, 2007

Robust Adders Based on Quantum-Dot Cellular Automata.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Scalable FFT Processors and Pipelined Butterfly Units.
VLSI Signal Processing, 2006

Discrete cosine and sine transforms - regular algorithms and pipeline architectures.
Signal Processing, 2006

Software Pipelining Support for Transport Triggered Architecture Processors.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Software Implementation of WiMAX on the Sandbridge SandBlaster Platform.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Effects of Program Compression.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Evaluation of stride permutation networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Systematic approach for path metric access in Viterbi decoders.
IEEE Trans. Communications, 2005

Hardware Cost Estimation for Application-Specific Processor Design.
Proceedings of the Embedded Computer Systems: Architectures, 2005

Dictionary-based program compression on transport triggered architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Efficient byte permutation realizations for compact AES implementations.
Proceedings of the 13th European Signal Processing Conference, 2005

256-State Rate 1/2 Viterbi Decoder on TTA Processor.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

Complex Fixed-Point Matrix Inversion Using Transport Triggered Architecture.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Multiple-symbol parallel decoding for variable length codes.
IEEE Trans. VLSI Syst., 2004

Scalable FFT Processors and Pipelined Butterfly Units.
Proceedings of the Computer Systems: Architectures, 2004

Register-Based Permutation Networks for Stride Permutations.
Proceedings of the Computer Systems: Architectures, 2004

Direct versus iterative methods for fixed-point implementation of matrix inversion.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A low-power fractional decimator architecture for an IF-sampling dual-mode receiver.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

VLSI-efficient implementation of full adder-based median filter.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Roles of pulse position modulation on intrachannel nonlinearities affected high-bit-rate optic fiber channel.
Proceedings of IEEE International Conference on Communications, 2004

Implementation of two-dimensional discrete cosine transform and its inverse.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

Evolved gate arrays for image restoration.
Proceedings of the IEEE Congress on Evolutionary Computation, 2004

Stride Permutation Networks for Array Processors.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
Multistage interconnection networks for parallel Viterbi decoders.
IEEE Trans. Communications, 2003

FPGA-Based Variable Length Decoders.
Proceedings of the IFIP VLSI-SoC 2003, 2003

In-Place Storage of Path Metrics in Viterbi Decoders.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Parallel memory access in turbo decoders.
Proceedings of the IEEE 14th International Symposium on Personal, 2003

On allocation of turbo decoder iterations.
Proceedings of the IEEE 14th International Symposium on Personal, 2003

Mapping Action Systems to Hardware Descriptions.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2003

Evaluating Template-Based Instruction Compression on Transport Triggered Architectures.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

Conflict-free parallel memory access scheme for FFT processors.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Parallel iterations for recursive median filter.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A recurrent neural network for 1-D phase retrieval.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002
Register-based reordering networks for matrix transpose.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Parallel Multiple-Symbol Variable-Length Decoding.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001
Implementing reactive closed-system specifications.
J. Network and Computer Applications, 2001

Pipeline architecture for DCT/IDCT.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Register-based multi-port perfect shuffle networks.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Multi-port interconnection networks for radix-R algorithms.
Proceedings of the IEEE International Conference on Acoustics, 2001

2000
Constant geometry algorithm for discrete cosine transform.
IEEE Trans. Signal Processing, 2000

Parallel, memory access schemes for H.263 encoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Scalable interconnection networks for partial column array processor architectures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Pipeline architecture for 8×8 discrete cosine transform.
Proceedings of the IEEE International Conference on Acoustics, 2000

Pipelined architecture for inverse discrete cosine transform.
Proceedings of the 10th European Signal Processing Conference, 2000

1999
Safety, liveness and real-time in embedded system design.
J. Network and Computer Applications, 1999

Distance Transform Algorithm for Bit-Serial SIMD Architectures.
Computer Vision and Image Understanding, 1999

Hardware architecture for real-time distance transform.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999

1994
SIMD Parallel Calculation of Distance Transformations.
Proceedings of the Proceedings 1994 International Conference on Image Processing, 1994

1988
TAGIPS, An Adaptable Parallel Processor for Imaging Applications.
Proceedings of IAPR Workshop on Computer Vision, 1988


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