Jarno K. Tanskanen

According to our database1, Jarno K. Tanskanen authored at least 10 papers between 1999 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2009
Parallel Memory Architecture for Application-Specific Instruction-Set Processors.
J. Signal Process. Syst., 2009

2007
Parallel Memory Architecture for TTA Processor.
Proceedings of the Embedded Computer Systems: Architectures, 2007

2005
On Design of Parallel Memory Access Schemes for Video Coding.
J. VLSI Signal Process., 2005

2004
Parallel memory architectures for video coding.
PhD thesis, 2004

Scalable Parallel Memory Architectures for Video Coding.
J. VLSI Signal Process., 2004

Byte and modulo addressable parallel memory architecture for video coding.
IEEE Trans. Circuits Syst. Video Technol., 2004

2002
Configurable parallel memory architecture for multimedia computers.
J. Syst. Archit., 2002

2000
Parallel, memory access schemes for H.263 encoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Verifying external data memory interface for H.263 video DSP with memory simulator.
Proceedings of the 10th European Signal Processing Conference, 2000

1999
Parallel Memories in Video Encoding.
Proceedings of the Data Compression Conference, 1999


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