Teruo Tanaka

Orcid: 0000-0002-5218-6607

According to our database1, Teruo Tanaka authored at least 22 papers between 1992 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Parallelization of Automatic Tuning for Hyperparameter Optimization of Pedestrian Route Prediction Applications using Machine Learning.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2023

2019
Time Segment Correction Method for Parallel Time Integration.
J. Inf. Process., 2019

Acceleration of Symmetric Sparse Matrix-Vector Product using Improved Hierarchical Diagonal Blocking Format.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2019

2018
Algebraic Multigrid Solver Using Coarse Grid Aggregation with Independent Aggregation.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

2017
D-Spline Performance Tuning Method Flexibly Responsive to Execution Time Perturbation.
Proceedings of the Parallel Processing and Applied Mathematics, 2017

Fast Multidimensional Performance Parameter Estimation with Multiple One-Dimensional d-Spline Parameter Search.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

2016
Performance Analysis of SA-AMG Method by Setting Extracted Near-Kernel Vectors.
Proceedings of the High Performance Computing for Computational Science - VECPAR 2016, 2016

SIMD Parallel Sparse Matrix-Vector and Transposed-Matrix-Vector Multiplication in DD Precision.
Proceedings of the High Performance Computing for Computational Science - VECPAR 2016, 2016

Xev-GMP: Automatic Code Generation for GMP Multiple-Precision Code from C Code.
Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

2015
Performance Analysis of the Chebyshev Basis Conjugate Gradient Method on the K Computer.
Proceedings of the Parallel Processing and Applied Mathematics, 2015

Enhancement of Incremental Performance Parameter Estimation on ppOpen-AT.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

2014
Implementation of d-Spline-based incremental performance parameter estimation method with ppOpen-AT.
Sci. Program., 2014

Mixed-Precision AMG method for Many Core Accelerators.
Proceedings of the 21st European MPI Users' Group Meeting, 2014

2013
AVX Acceleration of DD Arithmetic Between a Sparse Matrix and Vector.
Proceedings of the Parallel Processing and Applied Mathematics, 2013

2006
<i>d-Spline</i> Based Incremental Parameter Estimation in Automatic Performance Tuning.
Proceedings of the Applied Parallel Computing. State of the Art in Scientific Computing, 2006

1998
Dynamic Gateways: A Novel Approach to Improve Networking Performance and Availability on Parallel Servers.
Proceedings of the High-Performance Computing and Networking, 1998

1997
Deadlock-Free Fault-tolerant Routing in the Multi-dimensional Crossbar Network and Its Implementation for the Hitachi SR2201.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

1994
An interprocessor memory access arbitrating scheme for the S-3800 vector supercomputer.
Proceedings of the International Symposium on Parallel Architectures, 1994

Distributed storage control unit for the Hitachi S-3800 multivector supercomputer.
Proceedings of the 8th international conference on Supercomputing, 1994

1993
Scalable Parallel Memory Architecture with a Skew Scheme.
Proceedings of the 7th international conference on Supercomputing, 1993

Parallel Processing Architecture for the Hitachi S-3800 Shared-Memory Vector Multiprocessor.
Proceedings of the 7th international conference on Supercomputing, 1993

1992
Reducing Network Hardware Quantity by Employing Multi-Processor Cluster Structure in Distributed Memory Parallel Processors.
Proceedings of the Parallel Processing: CONPAR 92, 1992


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