Tetsuya Ichikawa

According to our database, Tetsuya Ichikawa authored at least 7 papers between 2000 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2007

Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level.

Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Leakage Analysis of DPA Countermeasures at the Logic Level.

Minoru Saeki, Daisuke Suzuki, Tetsuya Ichikawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2005

DPA Leakage Models for CMOS Logic Circuits.

Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa

Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

2004

Random Switching Logic: A Countermeasure against DPA based on Transition Probability.

Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa

IACR Cryptol. ePrint Arch., 2004

2002

The 128-Bit Block Cipher <i>Camellia</i>.

Kazumaro Aoki, Tetsuya Ichikawa, Masayuki Kanda, Mitsuru Matsui, Shiho Moriai, Junko Nakajima, Toshio Tokita

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

2000

Camellia: A 128-Bit Block Cipher Suitable for Multiple Platforms - Design and Analysis.

Kazumaro Aoki, Tetsuya Ichikawa, Masayuki Kanda, Mitsuru Matsui, Shiho Moriai, Junko Nakajima, Toshio Tokita

Proceedings of the Selected Areas in Cryptography, 7th Annual International Workshop, 2000

Hardware Evaluation of the AES Finalists.

Tetsuya Ichikawa, Tomomi Kasuya, Mitsuru Matsui

Proceedings of the Third Advanced Encryption Standard Candidate Conference, 2000