Daisuke Suzuki

According to our database1, Daisuke Suzuki authored at least 66 papers between 2000 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Bibliography

2020
Bypassing Isolated Execution on RISC-V with Fault Injection.
IACR Cryptol. ePrint Arch., 2020

Photoplethysmographic Subject Identification by Considering Feature Values Derived from Heartbeat and Respiration.
Proceedings of the 42nd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2020

2019
Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices.
Microelectron. J., 2019

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.
IEEE J. Solid State Circuits, 2019

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A Low-Cost Replica-Based Distance-Spoofing Attack on mmWave FMCW Radar.
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019

2018
SAEB: A Lightweight Blockcipher-Based AEAD Mode of Operation.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Aggregation of Charged Microgels by Relatively Diamagnetic Assembly.
Proceedings of the International Symposium on Micro-NanoMechatronics and Human Science, 2018

Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

Sensor CON-Fusion: Defeating Kalman Filter in Signal Injection Attack.
Proceedings of the 2018 on Asia Conference on Computer and Communications Security, 2018

2017
Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme.
IEICE Trans. Inf. Syst., 2017

Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing.
Proc. IEEE, 2016

Asymmetric Leakage from Multiplier and Collision-Based Single-Shot Side-Channel Attack.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Zero-cross switching control of halogen lamp heater with delta-sigma modulator.
Proceedings of the IECON 2016, 2016

A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Light-Weight Single Image Super-Resolution via Pattern-wise Regression Function.
Proceedings of the Digital Photography and Mobile Imaging XII, 2016

2015
Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.
IEEE J. Solid State Circuits, 2015

Reversing stealthy dopant-level circuits.
J. Cryptogr. Eng., 2015

Faster Enumeration of All Maximal Cliques in Unit Disk Graphs Using Geometric Structure.
IEICE Trans. Inf. Syst., 2015

Two Operands of Multipliers in Side-Channel Attack.
IACR Cryptol. ePrint Arch., 2015

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.
Proceedings of the Symposium on VLSI Circuits, 2015

Development of the Multi-dimensional Robot Attitude Scale: Constructs of People's Attitudes Towards Domestic Robots.
Proceedings of the Social Robotics - 7th International Conference, 2015

Design of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

PUF as a sensor.
Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
On measurable side-channel leaks inside ASIC design primitives.
J. Cryptogr. Eng., 2014

Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure.
IEICE Electron. Express, 2014

2013
Using Pulse Laser Processing to Shape Cutting Edge of PcBN Tool for High-Precision Turning of Hardened Steel.
Int. J. Autom. Technol., 2013

Metastable Ordered Phase Formation in CoPt and Co<sub>3</sub>Pt Alloy Thin Films Epitaxially Grown on Single-Crystal Substrates.
IEICE Trans. Electron., 2013

Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications.
IEICE Electron. Express, 2013

Cross-regional comparative study of dimensions of people's attitudes toward robots.
Proceedings of the IEEE International Symposium on Robot and Human Interactive Communication, 2013

A visibility improvement technique for fog images suitable for real-time application.
Proceedings of the Real-Time Image and Video Processing 2013, 2013

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Glitch PUF: Extracting Information from Usually Unwanted Glitches.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Dimensions of people's attitudes toward robots.
Proceedings of the International Conference on Human-Robot Interaction, 2012

Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI.
Proceedings of the 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2012

2011
How to Decide Selection Functions for Power Analysis: From the Viewpoint of Hardware Architecture of Block Ciphers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

2010
Phototactic and Chemotactic Signal Transduction by Transmembrane Receptors and Transducers in Microorganisms.
Sensors, 2010

A Design Methodology for a DPA-Resistant Circuit with RSL Techniques.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

High-Speed Passphrase Search System for PGP.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Increasing the Strength of Odors Produced by an Odor-Emitting Technology Using Odor Capsules.
IEICE Trans. Inf. Syst., 2010

Simultaneous detection of breath and alcohol using breath-alcohol sensor for prevention of drunk driving.
IEICE Electron. Express, 2010

The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2010

2009
Olfaction Presentation System Using Odor Scanner and Odor-Emitting Apparatus Coupled with Chemical Capsules of Alginic Acid Polymer.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A Study of Auditory Warning Signals for the Design Guidelines of Man-Machine Interfaces.
Proceedings of the Human Interface and the Management of Information. Information and Interaction, 2009

Complementary logics vs masked logics: Which countermeasure is a better selection?
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

2008
An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Security Evaluations of MRSL and DRSL Considering Signal Delays.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

High-Speed Search System for PGP Passphrases.
Proceedings of the Cryptology and Network Security, 7th International Conference, 2008

2007
Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Leakage Analysis of DPA Countermeasures at the Logic Level.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Pulse-Width Modulation with Current Uniformization for TFT-OLEDs.
IEICE Trans. Electron., 2007

How to Maximize the Potential of FPGA Resources for Modular Exponentiation.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2007

2006
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

Word Vectors and Two Kinds of Similarity.
Proceedings of the ACL 2006, 2006

2005
DPA Leakage Models for CMOS Logic Circuits.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

2004
Random Switching Logic: A Countermeasure against DPA based on Transition Probability.
IACR Cryptol. ePrint Arch., 2004

2002
Two-dimensional mapping of impedance magnetocardiograms.
IEEE Trans. Biomed. Eng., 2002

A high-level synthesis method for simultaneous placement and scheduling considering data communication delay.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2000
A Supporting System for Colored Knitting Design.
Proceedings of the Intelligent Problem Solving, 2000


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