Thomas Lenart

According to our database1, Thomas Lenart authored at least 14 papers between 2003 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2009
Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP Applications.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

2008
Design of Reconfigurable Hardware Architectures for Real-time Applications.
PhD thesis, 2008

A Hardware Acceleration Platform for Digital Holographic Imaging.
J. Signal Process. Syst., 2008

Modeling and exploration of a reconfigurable architecture for digital holographic imaging.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Modelling and exploration of a reconfigurable array using systemC TLM.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

2007
Accelerating Vector Operations by Utilizing Reconfigurable Coprocessor Architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Implementing the G.723.1 Speech Codec Using a Coarse-Grained Reconfigurable Coprocessor.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

2006
Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores.
IEEE Trans. Very Large Scale Integr. Syst., 2006

2005
A Complete MP3 Decoder on a Chip.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

Xstream - a hardware accelerator for digital holographic imaging.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

2003
Teaching Digital HW-Design by Implementing a Complete MP3 Decoder.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

A 2048 complex point FFT processor using a novel data scaling approach.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Accelerating signal processing algorithms in digital holography using an FPGA platform.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003


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