Peter Nilsson

Affiliations:
  • Lund University, Sweden


According to our database1, Peter Nilsson authored at least 67 papers between 1993 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2018
The Harmonized Parabolic Synthesis Methodology for Hardware Efficient Function Generation with Full Error Control.
J. Signal Process. Syst., 2018

2016
A Digitally Assisted Nonlinearity Mitigation System for Tunable Channel Select Filters.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Combining the parabolic synthesis methodology with second-degree interpolation.
Microprocess. Microsystems, 2016

2015
Low power unrolled CORDIC architectures.
Proceedings of the Nordic Circuits and Systems Conference, 2015

Session 8 overview: Low-power digital techniques: Energy-efficient digital.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
Improved Matching-Pursuit Implementation for LTE Channel Estimation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Low complexity adaptive channel estimation and QR decomposition for an LTE-A downlink.
Proceedings of the 25th IEEE Annual International Symposium on Personal, 2014

Hardware implementation of the exponential function using Taylor series.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014

Ultra low power transceivers for wireless sensors and body area networks.
Proceedings of the 8th International Symposium on Medical Information and Communication Technology, 2014

A digital baseband for low power FSK based receiver in 65 nm CMOS.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Supply-voltage down conversion for digital CMOS designs.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Lessons from ten years of the international master's program in System-on-Chip.
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014

2013
VLSI Implementation of a Soft-Output Signal Detector for Multimode Adaptive Multiple-Input Multiple-Output Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Ultra low energy design exploration of digital decimation filters in 65 nm dual-V<sub>T</sub> CMOS in the sub-V<sub>T</sub> domain.
Microprocess. Microsystems, 2013

Power savings in digital filters for wireless communication.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

A high-speed QR decomposition processor for carrier-aggregated LTE-A downlink systems.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012
Low-Complexity Likelihood Information Generation for Spatial-Multiplexing MIMO Signal Detection.
IEEE Trans. Veh. Technol., 2012

Area-Efficient Configurable High-Throughput Signal Detector Supporting Multiple MIMO Modes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A Receiver Architecture for Devices in Wireless Body Area Networks.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A unified multi-mode MIMO detector with soft-output.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
Low complexity soft-output signal detector for spatial-multiplexing MIMO system.
Proceedings of the IEEE 22nd International Symposium on Personal, 2011

On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systems.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Improved matching pursuit algorithm and architecture for LTE Channel Estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Detecting multi-mode MIMO signals: Algorithm and architecture design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A VLSI implementation of logarithmic and exponential functions using a novel parabolic synthesis methodology compared to the CORDIC algorithm.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

Power reductions in unrolled CORDIC architectures.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

Ultra low power hardware for computing Squared Euclidean Distances.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
Automatic Discovery of Feature Sets for Dependency Parsing.
Proceedings of the COLING 2010, 2010

2009
Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS.
VLSI Design, 2009

Hardware Architecture of an SVD based MIMO OFDM Channel Estimator.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Parabolic Synthesis Methodology Implemented on the Sine Function.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Complexity reductions in unrolled CORDIC architectures.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
An Embedded Real-Time Surveillance System: Implementation and Evaluation.
J. Signal Process. Syst., 2008

Arithmetic reduction of adder leakage in nanoscale CMOS.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Reducing Leakage Power in Fixed Coefficient Arithmetic.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Hardware architecture for matrix factorization in mimo receivers.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
A VLSI Architecture of the Square Root Algorithm for V-BLAST Detection.
J. VLSI Signal Process., 2006

Algorithm and implementation of the K-best sphere decoding for MIMO detection.
IEEE J. Sel. Areas Commun., 2006

Arithmetic Reduction of the Static Power Consumption in Nanoscale CMOS.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Background Segmentation Beyond RGB.
Proceedings of the Computer Vision, 2006

2005
A low complexity architecture for binary image erosion and dilation using structuring element decomposition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A 53.3 Mb/s 4×4 16-QAM MIMO decoder in 0.35-µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
A digitally controlled PLL for SoC applications.
IEEE J. Solid State Circuits, 2004

Reduced complexity Schnorr-Euchner decoding algorithms for MIMO systems.
IEEE Commun. Lett., 2004

VLSI implementation issues of lattice decoders for MIMO systems.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A generic transmitter for wireless OFDM systems.
Proceedings of the IEEE 14th International Symposium on Personal, 2003

A VLSI implementation of MIMO detection for future wireless communications.
Proceedings of the IEEE 14th International Symposium on Personal, 2003

Teaching Digital HW-Design by Implementing a Complete MP3 Decoder.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

A digitally controlled PLL for digital SOCs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001
SOCWARE: A New Swedish Design Cluster for System-on-Chip.
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

Application of Software design patterns to DSP library design.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Dual supply-voltage scaling for reconfigurable SoC's.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
A digitally controlled low-power clock multiplier for globally asynchronous locally synchronous designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

An OFDM timing synchronization ASIC.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999
Globally asynchronous locally synchronous architecture for large high-performance ASICs.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Silicon realization of an OFDM synchronization algorithm.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style.
Proceedings of the 36th Conference on Design Automation, 1999

1998
An Efficient Implementation OF Bandlimited Dithering.
Wirel. Pers. Commun., 1998

Hardware implementation aspects of a detector based on successive interference cancellation in a DS/CDMA system.
Proceedings of the 9th IEEE International Symposium on Personal, 1998

1997
A custom digital intermediate frequency filter for the American mobile telephone system.
IEEE J. Solid State Circuits, 1997

1996
A monolithic digital clock-generator for on-chip clocking of custom DSP's.
IEEE J. Solid State Circuits, 1996

Design of a fast and area efficient filter.
Proceedings of the 8th European Signal Processing Conference, 1996

1994
A Bit-Serial CMOS Digital IF-Filter for Mobile Radio Using an On-Chip Clock.
Proceedings of the Mobile Communications: Advanced Systems and Components, 1994

1993
A GSM speech coder implemented on a customized processor architecture.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

How to Manage Complexity in Inter-Organizational Information Systems (IOIS) - Some Preliminary Conclusions.
Proceedings of the Decision Support in Public Administration, 1993


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