Viktor Öwall
Orcid: 0000-0002-3368-1207
According to our database1,
Viktor Öwall
authored at least 114 papers
between 1993 and 2021.
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Bibliography
2021
The Effect of Coupling Memory and Block Length on Spatially Coupled Serially Concatenated Codes.
Proceedings of the 93rd IEEE Vehicular Technology Conference, 2021
2020
Angular-Domain Massive MIMO Detection: Algorithm, Implementation, and Design Tradeoffs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
2019
A Low Latency FFT/IFFT Architecture for Massive MIMO Systems Utilizing OFDM Guard Bands.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
An Area-Efficient On-Chip Memory System for Massive MIMO Using Channel Data Compression.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
A 1.8Gb/s 70.6pJ/b 128×16 link-adaptive near-optimal massive MIMO detector in 28nm UTBB-FDSOI.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE Global Conference on Signal and Information Processing, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
The World's First Real-Time Testbed for Massive MIMO: Design, Implementation, and Validation.
IEEE Access, 2017
Reducing On-Chip Memory for Massive MIMO Baseband Processing Using Channel Compression.
Proceedings of the 86th IEEE Vehicular Technology Conference, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
Implementation of Low-Latency Signal Processing and Data Shuffling for TDD Massive MIMO Systems.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
2015
Energy Efficient Group-Sort QRD Processor With On-Line Update for MIMO Channel Pre-Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A low-latency high-throughput soft-output signal detector for spatial multiplexing MIMO systems.
Microprocess. Microsystems, 2015
Microprocess. Microsystems, 2015
Circuits Syst. Signal Process., 2015
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
A 350μW Sign-Bit architecture for multi-parameter estimation during OFDM acquisition in 65nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
A Square-Root-Free Matrix Decomposition Method for Energy-Efficient Least Square Computation on Embedded Systems.
IEEE Embed. Syst. Lett., 2014
Implementation of a novel architecture for DFT-based channel estimators in OFDM systems.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014
Proceedings of the 8th International Symposium on Medical Information and Communication Technology, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 2014 IEEE GLOBECOM Workshops, Austin, TX, USA, December 8-12, 2014, 2014
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014
2013
VLSI Implementation of a Soft-Output Signal Detector for Multimode Adaptive Multiple-Input Multiple-Output Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
An 0.8-mm<sup>2</sup> 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS.
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE Wireless Communications and Networking Conference (WCNC), 2013
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013
Implementation of a highly-parallel soft-output MIMO detector with fast node enumeration.
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013
Proceedings of the 2013 NORCHIP, Vilnius, Lithuania, November 11-12, 2013, 2013
Analog and digital approaches for an energy efficient low complexity channel decoder.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 20th IEEE International Conference on Electronics, 2013
2012
High-Level Energy Estimation in the Sub-V$_{{\rm T}}$ Domain: Simulation and Measurement of a Cardiac Event Detector.
IEEE Trans. Biomed. Circuits Syst., 2012
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
Energy efficient MIMO channel pre-processor using a low complexity on-line update scheme.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012
Mapping channel estimation and MIMO detection in LTE-advanced on a reconfigurable cell array.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
A 0.8 mm<sup>2</sup> 9.6 mW implementation of a multicarrier Faster-than-Nyquist signaling iterative decoder in 65nm CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
Multicarrier Faster-Than-Nyquist Transceivers: Hardware Architecture and Performance Analysis.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Proceedings of the 2011 IEEE Wireless Communications and Networking Conference, 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Complexity analysis of IOTA filter architectures in faster-than-Nyquist multicarrier systems.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier Systems.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Reconfigurable cell array for concurrent support of multiple radio standards by flexible mapping.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
An analog (7, 5) convolutional decoder in 65 nm CMOS for low power wireless applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Microprocess. Microsystems, 2010
Proceedings of the 71st IEEE Vehicular Technology Conference, 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
A sign-bit auto-correlation architecture for fractional frequency offset estimation in OFDM.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of IEEE International Conference on Communications, 2010
2009
Binary Morphology With Spatially Variant Structuring Elements: Algorithm and Architecture.
IEEE Trans. Image Process., 2009
A Hardware Architecture for Real-Time Video Segmentation Utilizing Memory Reduction Techniques.
IEEE Trans. Circuits Syst. Video Technol., 2009
Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP Applications.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V<sub><i>t</i></sub> Domain By Architectural Folding.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
J. Signal Process. Syst., 2008
J. Signal Process. Syst., 2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Low-Complexity Binary Morphology Architectures With Flat Rectangular Structuring Elements.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Modeling and exploration of a reconfigurable architecture for digital holographic imaging.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008
A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
2007
Survivor Path Processing in Viterbi Decoders Using Register Exchange and Traceforward.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Accelerating Vector Operations by Utilizing Reconfigurable Coprocessor Architectures.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Implementation of a Labeling Algorithm based on Contour Tracing with Feature Extraction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Implementing the G.723.1 Speech Codec Using a Coarse-Grained Reconfigurable Coprocessor.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
Proceedings of the Advanced Video and Signal Based Surveillance, 2006
2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
Proceedings of the IEEE 16th International Symposium on Personal, 2005
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A dual-mode wavelet based R-wave detector using single-V<sub>t</sub> for leakage reduction [cardiac pacemaker applications].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Hardware accelerator design for video segmentation with multi-modal background modelling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A low complexity architecture for binary image erosion and dilation using structuring element decomposition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
2004
IEEE Commun. Lett., 2004
A wavelet based R-wave detector for cardiac pacemakers in 0.35 CMOS technology.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
FPGA implementation of controller-datapath pair in custom image processor design.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004
2003
Proceedings of the IEEE 14th International Symposium on Personal, 2003
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
Design and ASIC performance analysis of a reconfigurable digital filter for a UMTS application.
Proceedings of the Seventh International Symposium on Signal Processing and Its Applications, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Implementation of a highly scalable architecture for fast inversion of triangular matrices.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Accelerating signal processing algorithms in digital holography using an FPGA platform.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
FPGA implementation of real-time image convolutions with three level of memory hierarchy.
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
Proceedings of the ESSCIRC 2003, 2003
2001
QRS detection for pacemakers in a noisy environment using a time lagged artificial neural network.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
IEEE J. Solid State Circuits, 2000
Co-optimization of FFT and FIR in a delayless acoustic echo canceller implementation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
A Custom Image Convolution DSP with a Sustained Calculation Capacity of >1 GMAC/s and Low I/O Bandwidth.
J. VLSI Signal Process., 1999
1998
Hardware implementation aspects of a detector based on successive interference cancellation in a DS/CDMA system.
Proceedings of the 9th IEEE International Symposium on Personal, 1998
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998
1994
1993
A GSM speech coder implemented on a customized processor architecture.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993