Tiago Dias

Orcid: 0000-0001-7445-5823

Affiliations:
  • INESC-ID, Lisbon, Portugal


According to our database1, Tiago Dias authored at least 23 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Neural Network Predictor for Fast Channel Change on DVB Set-Top-Boxes.
Proceedings of the Design and Architecture for Signal and Image Processing, 2023

2022
A Multi-supplier Collaborative Monitoring Framework for Informatics System of Systems.
Proceedings of the Collaborative Networks in Digitalization and Society 5.0, 2022

2021
Open and Collaborative Micro Services in Digital Transformation.
Proceedings of the Smart and Sustainable Collaborative Networks 4.0, 2021

A Collaborative Cyber-Physical Microservices Platform - the SITL-IoT Case.
Proceedings of the Smart and Sustainable Collaborative Networks 4.0, 2021

2019
Adaptive Integration of IoT with Informatics Systems for Collaborative Industry: The SITL-IoT Case.
Proceedings of the Collaborative Networks and Digital Transformation, 2019

2015
High performance IP core for HEVC quantization.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs.
EURASIP J. Adv. Signal Process., 2014

2013
Scalable Unified Transform Architecture for Advanced Video Coding Embedded Systems.
Int. J. Parallel Program., 2013

Gesture interaction system for social web applications on smart TVs.
Proceedings of the Open research Areas in Information Retrieval, 2013

High performance multi-standard architecture for DCT computation in H.264/AVC High Profile and HEVC codecs.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
High Performance Unified Architecture for Forward and Inverse Quantization in H.264/AVC.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
A flexible architecture for the computation of direct and inverse transforms in H.264/AVC video codecs.
IEEE Trans. Consumer Electron., 2011

High throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systems.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

2010
H.264/AVC framework for multi-core embedded video encoders.
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

Integrated accelerator architecture for DNA sequences alignment with enhanced traceback phase.
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010

Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

2008
Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007
Reconfigurable architectures and processors for real-time video motion estimation.
J. Real Time Image Process., 2007

Adaptive Motion Estimation Processor for Autonomous Video Devices.
EURASIP J. Embed. Syst., 2007

2006
Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Application Specific Instruction Set Processor for Adaptive Video Motion Estimation.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005
Efficient VLSI Architecture for Real-Time Motion Estimation in Advanced Video Coding.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

2003
Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003


  Loading...