Paulo F. Flores
Orcid: 0000-0003-2970-3589
According to our database1,
Paulo F. Flores
authored at least 66 papers
between 1997 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
-
on dl.acm.org
On csauthors.net:
Bibliography
2023
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
CoRR, 2023
Architectural Exploration for Energy-Efficient LMS and NLMS Adaptive Filters VLSI Design.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
2020
Radix-2<sup> <i>r</i> </sup> recoding with common subexpression elimination for multiple constant multiplication.
IET Circuits Devices Syst., 2020
2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
2016
A novel method for the approximation of multiplierless constant matrix vector multiplication.
EURASIP J. Embed. Syst., 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Signal Process., 2015
Approximation of multiple constant multiplications using minimum look-up tables on FPGA.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
ACM Trans. Design Autom. Electr. Syst., 2014
Circuits Syst. Signal Process., 2014
ECHO: A novel method for the multiplierless design of constant array vector multiplication.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Optimized ASIP architecture for compressed BWT-indexed search in bioinformatics applications.
Proceedings of the International Conference on High Performance Computing & Simulation, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
Configurable and scalable class of high performance hardware accelerators for simultaneous DNA sequence alignment.
Concurr. Comput. Pract. Exp., 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the Twenty-Sixth International Florida Artificial Intelligence Research Society Conference, 2013
Exploration of tradeoffs in the design of integer cosine transforms for image compression.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
2012
Integrated Hardware Architecture for Efficient Computation of the $n$-Best Bio-Sequence Local Alignments in Embedded Platforms.
IEEE Trans. Very Large Scale Integr. Syst., 2012
ACM Trans. Design Autom. Electr. Syst., 2012
Hardware accelerator architecture for simultaneous short-read DNA sequences alignment with enhanced traceback phase.
Microprocess. Microsystems, 2012
High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications.
Integr., 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Finding the optimal tradeoff between area and delay in multiple constant multiplications.
Microprocess. Microsystems, 2011
Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays.
J. Low Power Electron., 2011
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Design of low-power multiple constant multiplications using low-complexity minimum depth operations.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Optimization of gate-level area in high throughput Multiple Constant Multiplications.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
Search algorithms for the multiple constant multiplications problem: Exact and approximate.
Microprocess. Microsystems, 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Integrated accelerator architecture for DNA sequences alignment with enhanced traceback phase.
Proceedings of the 2010 International Conference on High Performance Computing & Simulation, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
ACM Trans. Design Autom. Electr. Syst., 2009
2008
Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Minimum number of operations under a general number representation for digital filter synthesis.
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
Proceedings of the 44th Design Automation Conference, 2007
2006
Exploiting general coefficient representation for the optimal sharing of partial products in MCMs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming.
Proceedings of the 43rd Design Automation Conference, 2006
2005
An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005
2001
ACM Trans. Design Autom. Electr. Syst., 2001
1999
Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
1997
Proceedings of the 9th International Conference on Tools with Artificial Intelligence, 1997