Tiago S. Curtinhas

According to our database, Tiago S. Curtinhas authored at least 12 papers between 2013 and 2021.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2021

A novel approach for the design of low-power pipelined synchronous systems operating in double-edge of the clock.

Orlando Verducci Jr., Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista, Tiago S. Curtinhas

Microelectron. J., 2021

2019

A State Assignment Method for Extended Burst-Mode gC Finite State Machines Based on Genetic Algorithm.

Tiago S. Curtinhas, Duarte Lopes de Oliveira, Gracieth Cavalcanti Batista, Vitor L. V. Torres, Leonardo Romano

Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

2018

A Novel Tool for Synthesis by Direct Mapping of Asynchronous Circuits from Extended STG Specifications.

Felipe Mendes, Tiago S. Curtinhas, Duarte Lopes de Oliveira, Higor A. Delsoto, Lester de Abreu Faria

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

A novel state assignment method for XBM AFSMs without the essential hazard assumption.

Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lucas Moura Santana, Lester de Abreu Faria

Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

2017

Implementation of Locally-Clocked XBM State Machines on FPGAs Using Synchronous CAD Tools.

Felipe Tuyama De Faria Barbosa, Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lester de Abreu Faria, Jocemar Francisco De Souza Luciano

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016

A design flow for locally-clocked XBM asynchronous state machines using synchronous CAD tools.

Duarte Lopes de Oliveira, Felipe Tuyama De Faria Barbosa, Tiago S. Curtinhas, Lester de Abreu Faria, Jocemar F. Sousa

Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015

Minimization and Encoding of High Performance Asynchronous State Machines Based on Genetic Algorithm.

Tiago S. Curtinhas, Tassio Cortes Cavalcante, Duarte Lopes de Oliveira, Lester de Abreu Faria, Osamu Saotome

Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A novel asynchronous interface with pausible clock for partitioned synchronous modules.

Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lester de Abreu Faria, Leonardo Romano

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

2014

A novel State Assignment method for Extended Burst-Mode FSM design using Genetic Algorithm.

Tiago S. Curtinhas, Duarte Lopes de Oliveira, Lester de Abreu Faria, Osamu Saotome

Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers.

Tiago S. Curtinhas, Duarte Lopes de Oliveira, Diego Bompean, Lester de Abreu Faria, Leonardo Romano

Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

2013

Design of synchronous pipeline digital systems operating in double-edge of the clock.

Duarte Lopes de Oliveira, Tiago S. Curtinhas, Lester de Abreu Faria, Leonardo Romano

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Design of locally-clocked asynchronous finite state machines using synchronous CAD tools.

Duarte Lopes de Oliveira, Diego Bompean, Tiago S. Curtinhas, Lester de Abreu Faria

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013