Lester de Abreu Faria

Orcid: 0000-0003-1785-446X

Affiliations:
  • Technological Institute of Aeronautics-ITA-IEEA, Electronic Engineering Division, Brazil


According to our database1, Lester de Abreu Faria authored at least 26 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Generation of Realistic Synthetic Raw Radar Data for Automated Driving Applications using Generative Adversarial Networks.
CoRR, 2023

Exploiting GAN Capacity to Generate Synthetic Automotive Radar Data.
Proceedings of the 18th International Joint Conference on Computer Vision, 2023

A novel Conditional Generative Adversarial Networks for Automotive Radar Range-Doppler Targets Synthetic Generation.
Proceedings of the 25th IEEE International Conference on Intelligent Transportation Systems, 2023

2022
Facens Smart Campus Integrated Dashboard: A Use Case Applied for Energy Efficiency.
Proceedings of the IoT and WSN based Smart Cities: A Machine Learning Perspective, 2022

2021
A PWM Nie-Tan Type-Reducer Circuit for a Low-Power Interval Type-2 Fuzzy Controller.
IEEE Access, 2021

2020
Improving Teaching-Learning Process in MIL-STD-1553B Bus Classes Using a New Hybrid Web-Lab Methodology.
IEEE Trans. Educ., 2020

A framework to evaluate the environmental quality and simulate future scenarios of urban forests: atlantic forest case study.
Proceedings of the IEEE International Smart Cities Conference, 2020

2019
Low-Power Current-Mode Interval Type-2 Fuzzy Inference Engine Circuit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Low power membership function generator for interval type-2 fuzzy system.
J. Intell. Fuzzy Syst., 2019

2018
A novel fully-programmable analog fuzzifier architecture for interval type-2 fuzzy controllers using current steering mirrors.
J. Intell. Fuzzy Syst., 2018

A Novel Tool for Synthesis by Direct Mapping of Asynchronous Circuits from Extended STG Specifications.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

FPGA implementation of high-performance asynchronous pipelines with robust control.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

A novel state assignment method for XBM AFSMs without the essential hazard assumption.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

A design flow of asynchronous burst-mode circuits without fundamental-mode timing assumption.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

2017
Implementation of Locally-Clocked XBM State Machines on FPGAs Using Synchronous CAD Tools.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016
Software-Defined Radio design based on GALS architecture for FPGAs.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

FPGA implementation of optimized XBM specifications by transformation for AFSMs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

A design flow for locally-clocked XBM asynchronous state machines using synchronous CAD tools.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

2015
Minimization and Encoding of High Performance Asynchronous State Machines Based on Genetic Algorithm.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A novel asynchronous interface with pausible clock for partitioned synchronous modules.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

2014
Desenvolvimento de modelos de simulação para transistores MOS a temperaturas criogênicas (77K).
PhD thesis, 2014

A novel State Assignment method for Extended Burst-Mode FSM design using Genetic Algorithm.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

SICARELO: A tool for synthesis of locally-clocked extended burst-mode asynchronous Controllers.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

2013
Design of asynchronous systems on FPGA using direct mapping and synchronous specification.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Design of synchronous pipeline digital systems operating in double-edge of the clock.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Design of locally-clocked asynchronous finite state machines using synchronous CAD tools.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013


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