Lucas Moura Santana
Orcid: 0000-0002-1642-2465
According to our database1,
Lucas Moura Santana authored at least 7 papers
between 2018 and 2026.
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Bibliography
2026
11.5 A Compact 7b 175GS/s Linearized Time-Interleaved Slope ADC with Switched Input Buffers.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2023
A 70MHz Bandwidth Time-Interleaved Noise-Shaping SAR Assisted Delta Sigma ADC with Digital Cross-Coupling in 28nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
2022
A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS.
IEEE J. Solid State Circuits, 2022
2021
Proceedings of the 47th ESSCIRC 2021, 2021
2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
A novel state assignment method for XBM AFSMs without the essential hazard assumption.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
A design flow of asynchronous burst-mode circuits without fundamental-mode timing assumption.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018