Tianchen Ye

According to our database, Tianchen Ye authored at least 5 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A 4×106 Gb/s Mixed-Signal PAM-4 Transceivers for Optical Direct-Detect Applications With Adaptive Linearity Compensation in 28-nm CMOS.

Boyang Zhang, Tianchen Ye, Zhifei Wang, Xin Liu, Tianyuan Zhong, Ruixu Wang, Weixin Gai

IEEE Trans. Circuits Syst. II Express Briefs, May, 2025

A 50Gb/s Burst-Mode NRZ Receiver with 5-Tap FFE, 7-Tap DFE and 15ns Lock Time in 28nm CMOS for Symmetric 50G-PON.

Boyang Zhang, Tianchen Ye, Shuaizhe Ma, Tianyuan Zhong, Xin Liu, Feiyang Zhang, Bingyi Ye, Dan Li, Weixin Gai

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS.

Bingyi Ye, Tianchen Ye, Tianyuan Zhong, Zhiwen Huang, Lei Shen, Boyang Zhang, Dunshan Yu, Yandong He, Weixin Gai

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

A 64Gb/s/wire 10.5Tb/s/mm/Layer Single-Ended Simultaneous Bi-Directional Transceiver with Echo and Crosstalk Cancellation for a Die-to-Die Interface in 28nm CMOS.

Zhifei Wang, Zhiwen Huang, Tianchen Ye, Bingyi Ye, Fangzhu Li, Wei Wang, Dunshan Yu, Weixin Gai

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2024

A 200-Gb/s PAM-4 Transmitter with 1.6-Vppd Output Swing and Clock Skew Correction in 12-nm FinFET.

Boyang Zhang, Zhifei Wang, Zeze Feng, Tianchen Ye, Bingyi Ye, Zixu Wang, Weixin Gai

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024