Weixin Gai
Orcid: 0000-0002-7162-2427
According to our database1,
Weixin Gai
authored at least 37 papers
between 2003 and 2024.
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Bibliography
2024
A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS.
IEEE J. Solid State Circuits, January, 2024
2023
A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS.
IEEE J. Solid State Circuits, 2023
IEEE J. Solid State Circuits, 2023
A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A Residue Amplifier with 85 dB DC Gain and 15 GHz Closed-Loop Bandwidth for 14-Bit 3GSPS Pipeline ADC.
Circuits Syst. Signal Process., 2022
A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A High-Linearity 14GHz 7b Phase Interpolator for Ultra-High-Speed Wireline Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
2021
Microelectron. J., 2021
56 Gb/s PAM4 receiver with an overshoot compensation scheme in 28 nm CMOS technology.
Microelectron. J., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2019
An 8-12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Design of an Adaptive Loop Gain Controller Based on Auto-correlation Detection Scheme in All-Digital Phase-Locked Loop.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
An 8.52-11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 108fs<sub>rms</sub> 0.45mW 100MS/s 1.25MHz bandwidth multi-bit ΔΣ time-to-digital converter with dynamic element matching.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2016
PAM4 receiver with adaptive threshold voltage and adaptive decision feedback equalizer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A novel 6-Gbps half-rate SST transmitter with impedance calibration and adjustable pre-emphasis.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A novel frequency search algorithm to achieve fast locking without phase tracking in ADPLL.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A 2.7-GHz digitally-controlled ring oscillator with supply sensitivity of 0.0014%-fDCO/1%-VDD using digital current-regulated tuning.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2009
A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control.
IEEE J. Solid State Circuits, 2009
A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2007
A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2003
A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems.
J. VLSI Signal Process., 2003