Tianci Cai

According to our database¹, Tianci Cai authored at least 3 papers in 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

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2025

A High Performance Dual-Wordline RRAM Macro with Replica Bitline Delay Control Circuit.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A Refresh-Reduction Digital eDRAM CIM Macro using Asymmetric Error Tolerance Scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

SRIF: Energy- and Area-Efficient Soft Reset Integrate-and-Fire Neuron for High-Accuracy Spiking Neural Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

Tianci Cai

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