According to our database1, Tim Thielemans authored at least 3 papers between 2018 and 2020.
Legend:Book In proceedings Article PhD thesis Other
A 4V-0.55V Input Fully Integrated Switched-Capacitor Converter Enabling Dynamic Voltage Domain Stacking and Achieving 80.1% Average Efficiency.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
A Fully-Integrated 6: 1 Cascaded Switched-Capacitor DC-DC Converter Achieving 74% Efficiency at 0.1W/mm<sup>2</sup>.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019
A capacitive DC-DC converter for stacked loads with wide range DVS achieving 98.2% peak efficiency in 40nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018