Tim Thielemans

According to our database, Tim Thielemans authored at least 4 papers between 2018 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

A 240V to 47.5 V Fully Integrated Switched-Capacitor Converter in GaN Achieving 62.6% Efficiency at 220 mW/mm².

Bram Veraverbeke, Tim Thielemans, Tuur Van Daele, Filip Tavernier

Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

2020

A 4V-0.55V Input Fully Integrated Switched-Capacitor Converter Enabling Dynamic Voltage Domain Stacking and Achieving 80.1% Average Efficiency.

Tim Thielemans, Filip Tavernier

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019

A Fully-Integrated 6: 1 Cascaded Switched-Capacitor DC-DC Converter Achieving 74% Efficiency at 0.1W/mm².

Tuur Van Daele, Elly De Pelecijn, Tim Thielemans, Michiel Steyaert, Filip Tavernier

Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

2018

A capacitive DC-DC converter for stacked loads with wide range DVS achieving 98.2% peak efficiency in 40nm CMOS.

Tim Thielemans, Nicolas Butzen, Athanasios Sarafianos, Michiel Steyaert, Filip Tavernier

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018