Filip Tavernier

According to our database1, Filip Tavernier authored at least 30 papers between 2008 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
A 28μW 134dB DR 2nd-Order Noise-Shaping Slope Light-to-Digital Converter for Chest PPG Monitoring.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2020
A 119dB Dynamic Range Charge Counting Light-to-Digital Converter For Wearable PPG/NIRS Monitoring Applications.
IEEE Trans. Biomed. Circuits Syst., 2020

A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC With Analog-Digital Corrections in 28-nm CMOS.
IEEE J. Solid State Circuits, 2020

A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs.
IEEE J. Solid State Circuits, 2020

1310/1550 nm Optical Receivers With Schottky Photodiode in Bulk CMOS.
IEEE J. Solid State Circuits, 2020

A 4V-0.55V Input Fully Integrated Switched-Capacitor Converter Enabling Dynamic Voltage Domain Stacking and Achieving 80.1% Average Efficiency.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 1 GS/s Reconfigurable BW 2<sup>nd</sup>-Order Noise-Shaping Hybrid Voltage-Time Two-Step ADC Achieving 170.9 dB FoMS.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2019
A Wideband Low-Noise Variable-Gain Amplifier With a 3.4 dB NF and up to 45 dB Gain Tuning Range in 130-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 196μW, Reconfigurable Light-to-Digital Converter with 119dB Dynamic Range, for Wearable PPG/NIRS Sensors.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

A Fully-Integrated 6: 1 Cascaded Switched-Capacitor DC-DC Converter Achieving 74% Efficiency at 0.1W/mm<sup>2</sup>.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feed-Forward Ring Oscillator-Based TDCs.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

Optical Receiver with Schottky Photodiode and TIA with High Gain Amplifier in 28nm Bulk CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

2018
40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS.
IEEE J. Solid State Circuits, 2018

A 400GΩ Input-Impedance, 220MVpp Linear-Input-Range, 2.8Vpp CM-Interference-Tolerant Active Electrode for Non-Contact Capacitively Coupled ECG Acquisition.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A Charge-Sharing Bandpass Filter Topology with Boosted Q-Factor in 40-NM CMOS.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

A 1310/1550 nm Fully-Integrated Optical Receiver with Schottky Photodiode and Low-Noise Transimpedance Amplifier in 40 nm Bulk CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A capacitive DC-DC converter for stacked loads with wide range DVS achieving 98.2% peak efficiency in 40nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
Schottky diodes in 40nm bulk CMOS for 1310nm high-speed optical receivers.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2017

Modelling, design and characterization of Schottky diodes in 28nm bulk CMOS for 850/1310/1550nm fully integrated optical receivers.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

2016
10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
When hardware is free, power is expensive! Is integrated power management the solution?
Proceedings of the ESSCIRC Conference 2015, 2015

2010
A 5.5 Gbit/s optical receiver in 130 nm CMOS with speed-enhanced integrated photodiode.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009
High-Speed Optical Receivers With Integrated Photodiode in 130 nm CMOS.
IEEE J. Solid State Circuits, 2009

A low power, area efficient limiting amplifier in 90nm CMOS.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
A high-speed fully integrated optical receiver in standard 130nm CMOS.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Power efficient 4.5Gbit/s optical receiver in 130nm CMOS with integrated photodiode.
Proceedings of the ESSCIRC 2008, 2008


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