Michiel Steyaert

According to our database1, Michiel Steyaert authored at least 134 papers between 1993 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2003, "For contributions to the design of CMOS RF communications circuits.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2019
A Wideband Low-Noise Variable-Gain Amplifier With a 3.4 dB NF and up to 45 dB Gain Tuning Range in 130-nm CMOS.
IEEE Trans. on Circuits and Systems, 2019

A Fully Integrated Switched-Capacitor-Based AC-DC Converter for a 120 VRMS Mains Interface.
J. Solid-State Circuits, 2019

Design of Single-Topology Continuously Scalable-Conversion-Ratio Switched- Capacitor DC-DC Converters.
J. Solid-State Circuits, 2019

A Fully-Integrated 6: 1 Cascaded Switched-Capacitor DC-DC Converter Achieving 74% Efficiency at 0.1W/mm2.
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 13.5-Gb/s 5-mV-Sensitivity 26.8-ps-CLK-OUT Delay Triple-Latch Feedforward Dynamic Comparator in 28-nm CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

Optical Receiver with Schottky Photodiode and TIA with High Gain Amplifier in 28nm Bulk CMOS.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019

Advanced Multiphasing: Pushing the Envelope of Fully Integrated Power Conversion.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2018
40-nm CMOS Wideband High-IF Receiver Using a Modified Charge-Sharing Bandpass Filter to Boost Q-Factor.
IEEE Trans. on Circuits and Systems, 2018

A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS.
J. Solid-State Circuits, 2018

A Single-Topology Continuously-Scalable-Conversion-Ratio Fully Integrated Switched-Capacitor DC-DC Converter with 0-to-2.22V Output and 93% Peak-Efficiency.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A Charge-Sharing Bandpass Filter Topology with Boosted Q-Factor in 40-NM CMOS.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

A Fully Integrated Switched-Capacitor Based AC-DC Converter for a 120VRMS Mains Interface.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A 1310/1550 nm Fully-Integrated Optical Receiver with Schottky Photodiode and Low-Noise Transimpedance Amplifier in 40 nm Bulk CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A capacitive DC-DC converter for stacked loads with wide range DVS achieving 98.2% peak efficiency in 40nm CMOS.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
Design of Soft-Charging Switched-Capacitor DC-DC Converters Using Stage Outphasing and Multiphase Soft-Charging.
J. Solid-State Circuits, 2017

MIMO Switched-Capacitor DC-DC Converters Using Only Parasitic Capacitances Through Scalable Parasitic Charge Redistribution.
J. Solid-State Circuits, 2017

10.1 A 1.1W/mm2-power-density 82%-efficiency fully integrated 3∶1 Switched-Capacitor DC-DC converter in baseline 28nm CMOS using Stage Outphasing and Multiphase Soft-Charging.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Modelling, design and characterization of Schottky diodes in 28nm bulk CMOS for 850/1310/1550nm fully integrated optical receivers.
Proceedings of the 47th European Solid-State Device Research Conference, 2017

A 36.4dB SNDR @ 5GHz 1.25GS/s 7b 3.56mW single-channel SAR ADC in 28nm bulk CMOS.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Highly integrated wavelength-locked Si photonic ring transmitter using direct monitoring of drop-port OMA.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Fully integrated power management: The missing link?
Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2016
A Self-Calibrated Bang-Bang Phase Detector for Low-Offset Time Signal Processing.
IEEE Trans. on Circuits and Systems, 2016

Scalable Parasitic Charge Redistribution: Design of High-Efficiency Fully Integrated Switched-Capacitor DC-DC Converters.
J. Solid-State Circuits, 2016

Wavelength Locking of a Si Ring Modulator Using an Integrated Drop-Port OMA Monitoring Circuit.
J. Solid-State Circuits, 2016

12.2 A 94.6%-efficiency fully integrated switched-capacitor DC-DC converter in baseline 40nm CMOS using scalable parasitic charge redistribution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

MIMO Switched-Capacitor converter using only parasitic capacitance with Scalable Parasitic Charge Redistribution.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Fully Integrated Wide Input Voltage Range Capacitive DC-DC Converters: The Folding Dickson Converter.
J. Solid-State Circuits, 2015

A Light-Load-Efficient 11/1 Switched-Capacitor DC-DC Converter With 94.7% Efficiency While Delivering 100 mW at 3.3 V.
J. Solid-State Circuits, 2015

22.5 A 4×20Gb/s WDM ring-based hybrid CMOS silicon photonics transceiver.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

20.1 A light-load-efficient 11/1 switched-capacitor DC-DC converter with 94.7% efficiency while delivering 100mW at 3.3V.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

When hardware is free, power is expensive! Is integrated power management the solution?
Proceedings of the ESSCIRC Conference 2015, 2015

A folding dickson-based fully integrated wide input range capacitive DC-DC converter achieving Vout/2-resolution and 71% average efficiency.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

Wavelength locking of a Si ring modulator using an integrated drop-port OMA monitoring circuit.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014
Design of a frequency reference based on a PVT-independent transmission line delay.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

The folding dickson converter: A step towards fully integrated wide input range capacitive DC-DC converters.
Proceedings of the ESSCIRC 2014, 2014

2013
A 265 VRMS Mains Interface Integrated in 0.35 µm CMOS.
J. Solid-State Circuits, 2013

A 63, 000 Q-factor relaxation oscillator with switched-capacitor integrated error feedback.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Electronic dispersion correction circuit for Plastic Optical Fiber channels.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2013

2012
A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS.
J. Solid-State Circuits, 2012

Analog Building Blocks for Organic Smart Sensor Systems in Organic Thin-Film Transistor Technology on Flexible Plastic Foil.
J. Solid-State Circuits, 2012

1-1-1 MASH Δ Σ Time-to-Digital Converters With 6 ps Resolution and Third-Order Noise-Shaping.
J. Solid-State Circuits, 2012

On-chip gain reconfigurable 1.2V 24μW chopping instrumentation amplifier with automatic resistor matching in 0.13μm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

1D and 2D analog 1.5kHz air-stable organic capacitive touch sensors on plastic foil.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 265VRMS mains interface integrated in 0.35μm CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Dual-output capacitive DC-DC converter with power distribution regulator in 90 nm CMOS.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Monolithic integration of a class DE inverter for on-chip resonant DC-DC converters.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Trustworthy Genetic Programming-Based Synthesis of Analog Circuit Topologies Using Hierarchical Domain-Specific Building Blocks.
IEEE Trans. Evolutionary Computation, 2011

Multiple Event Time-to-Digital Conversion-Based Pulse Digitization for a 250 MHz Pulse Radio Ranging Application.
IEEE Trans. on Circuits and Systems, 2011

A Fully Integrated Delta Sigma ADC in Organic Thin-Film Transistor Technology on Flexible Plastic Foil.
J. Solid-State Circuits, 2011

Monolithic Capacitive DC-DC Converter With Single Boundary-Multiphase Control and Voltage Domain Stacking in 90 nm CMOS.
J. Solid-State Circuits, 2011

A 250mV 7.5μW 61dB SNDR CMOS SC ΔΣ modulator using a near-threshold-voltage-biased CMOS inverter technique.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 1.7mW 11b 1-1-1 MASH ΔΣ time-to-digital converter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 200GHz downconverter in 90nm CMOS.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

DC-DC converters: From discrete towards fully integrated CMOS.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

Differential input topologies with immunity to electromagnetic interference.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A monolithic 0.77W/mm2 power dense capacitive DC-DC step-down converter in 90nm Bulk CMOS.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

DC-DC converter assisted two-stage amplifier in organic thin-film transistor technology on foil.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A colpitts LC VCO with Miller-capacitance gm enhancing and phase noise reduction techniques.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

Circuit design in organic semiconductor technologies.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

An active guarding technique for substrate noise suppression on LC-tank oscillators.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 0.7mW 13b temperature-stable MASH ΔΣ TDC with delay-line assisted calibration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Kuijk Bandgap Voltage Reference With High Immunity to EMI.
IEEE Trans. on Circuits and Systems, 2010

EMI-Resistant CMOS Differential Input Stages.
IEEE Trans. on Circuits and Systems, 2010

A 10-Bit 1.6-GS/s 27-mW Current-Steering D/A Converter With 550-MHz 54-dB SFDR Bandwidth in 130-nm CMOS.
IEEE Trans. on Circuits and Systems, 2010

A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion.
IEEE Trans. on Circuits and Systems, 2010

Energy Supply and ULP Detection Circuits for an RFID Localization System in 130 nm CMOS.
J. Solid-State Circuits, 2010

A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS.
J. Solid-State Circuits, 2010

An analog organic first-order CT ΔΣ ADC on a flexible plastic substrate with 26.5dB precision.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

All-digital differential VCO-based A/D conversion.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Variation-Aware Structural Synthesis of Analog Circuits via Hierarchical Building Blocks and Structural Homotopy.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Erratum to "A 1-V 140-μW 88-dB Audio Sigma-Delta Modulator in 90-nm CMOS".
J. Solid-State Circuits, 2009

High-Speed Optical Receivers With Integrated Photodiode in 130 nm CMOS.
J. Solid-State Circuits, 2009

Erratum to "A 66 µW 86 ppm°C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM" [Jul 09 1990-2001].
J. Solid-State Circuits, 2009

A 66 µW 86 ppm° C Fully-Integrated 6 MHz Wienbridge Oscillator With a 172 dB Phase Noise FOM.
J. Solid-State Circuits, 2009

Design and Analysis of a 90 nm mm-Wave Oscillator Using Inductive-Division LC Tank.
J. Solid-State Circuits, 2009

A 2mm2 0.1-to-5GHz SDR receiver in 45nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Analysis of Fractional Spur Reduction using SigmaDelta-noise Cancellation in Digital-PLL.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Massively multi-topology sizing of analog integrated circuits.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized Gm-C Biquad in 0.13-mu m CMOS.
IEEE Trans. on Circuits and Systems, 2008

Design Considerations for Cascade Delta Sigma ADC's.
IEEE Trans. on Circuits and Systems, 2008

A 130 nm CMOS 6-bit Full Nyquist 3 GS/s DAC.
J. Solid-State Circuits, 2008

A Polar Modulator Using Self-Oscillating Amplifiers and an Injection-Locked Upconversion Mixer.
J. Solid-State Circuits, 2008

A low-power mixing DAC IR-UWB-receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A/D conversion using an Asynchronous Delta-Sigma Modulator and a time-to-digital converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A high-speed fully integrated optical receiver in standard 130nm CMOS.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Automated extraction of expert knowledge in analog topology selection and sizing.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A fully-integrated 0.18μm CMOS DC-DC step-down converter, using a bondwire spiral inductor.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

EMI resisting smart-power integrated LIN driver with reduced slope pumping.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A Design-Optimized Continuous-Time Delta-Sigma ADC for WLAN Applications.
IEEE Trans. on Circuits and Systems, 2007

A 2.45-GHz 0.13-µm CMOS PA With Parallel Amplification.
J. Solid-State Circuits, 2007

An EMI Resisting LIN Driver in 0.35-micron High-Voltage CMOS.
J. Solid-State Circuits, 2007

A 237mW aDSL2+ CO Line Driver in Standard 1.2V 0.13μ CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Analysis and Performance Comparison of a Cascade 3-1 Delta-Sigma Topology.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies.
Proceedings of the 44th Design Automation Conference, 2007

2006
A 7.5mW, 11-bit continuous-time sigma-delta A/D converter for WLAN applications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A High speed, Low Voltage to High Voltage Level Shifter in Standard 1.2V 0.13μm CMOS.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

A Continuous-Time Delta-Sigma Modulator for 802.11a/b/g WLAN Implemented with a Hierarchical Bottom-up Optimization Methodology.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

A Novel Bootstrapped Switch Design, Applied in a 400 MHz Clocked ΔΣ ADC.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard.
Proceedings of the 43rd Design Automation Conference, 2006

2005
An Efficient, Fully Parasitic-Aware Power Amplifier Design Optimization Tool.
IEEE Trans. on Circuits and Systems, 2005

Behavioral analysis of self-oscillating class D line drivers.
IEEE Trans. on Circuits and Systems, 2005

ESD-RF co-design methodology for the state of the art RF-CMOS blocks.
Microelectron. Reliab., 2005

2004
Positive feedback frequency compensation for low-voltage low-power three-stage amplifier.
IEEE Trans. on Circuits and Systems, 2004

A gradient-error and edge-effect tolerant switching scheme for a high-accuracy DAC.
IEEE Trans. on Circuits and Systems, 2004

A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits.
Microelectron. Reliab., 2004

Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbps.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Knowledge- and optimization-based design of RF power amplifiers.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A state-space behavioral model for CMOS class E power amplifiers.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

High frequency characterization and modelling of the parasitic RC performance of two terminal ESD CMOS protection devices.
Microelectron. Reliab., 2003

2002
CYCLONE: automated design and layout of RF LC-oscillators.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Design techniques for low power high bandwidth upconversion in CMOS.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Optimization of a fully integrated low power CMOS GPS receiver.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter.
Proceedings of the 2002 Design, 2002

Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter.
Proceedings of the 39th Design Automation Conference, 2002

CMOS: a paradigm for low power wireless?
Proceedings of the 39th Design Automation Conference, 2002

2001
A Layout-Aware Synthesis Methodology for RF Circuits.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000
An accurate statistical yield model for CMOS current-steering D/A converters.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

The extraction of transistor mismatch parameters: the CMOS current-steering D/A converter as a test structure.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

The optimization of GHz integrated CMOS quadrature VCO's based on a poly-phase filter loaded differential oscillator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Optimal RF design using smart evolutionary algorithms.
Proceedings of the 37th Conference on Design Automation, 2000

CYCLONE: automated design and layout of RF LC-oscillators.
Proceedings of the 37th Conference on Design Automation, 2000

1999
RF Communication Circuits.
Proceedings of the VLSI Handbook., 1999

1998
Theory of PLL fractional-N frequency synthesizers.
Wireless Networks, 1998

1996
Evaluation of CNN Template Robustness Towards VLSI Implementation.
I. J. Circuit Theory and Applications, 1996

1995
A high-level design and optimization tool for analog RF receiver front-ends.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994
Analogue CMOS VLSI Implementation of Cellular Neural Networks with Continuously Programmable Templates.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993
Low-voltage Analog CMOS Filter Design.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

High-performance CMOS continuous-time filters.
The Kluwer international series in engineering and computer science 223, Kluwer, ISBN: 978-0-7923-9339-9, 1993


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