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Ting-Feng Chang

According to our database1, Ting-Feng Chang authored at least 4 papers between 2011 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2015
Post-layout Redundant Via Insertion Approach Considering Multiple Via Configuration.
[BibTeX]
[DOI]
Tsang-Chi Kan
,
Shanq-Jang Ruan
,
Ting-Feng Chang
,
Shih-Hsien Yang
Circuits Syst. Signal Process., 2015

2013
Design of a Practical Nanometer-Scale Redundant Via-Aware Standard Cell Library for Improved Redundant Via1 Insertion Rate.
[BibTeX]
[DOI]
Tsang-Chi Kan
,
Shih-Hsien Yang
,
Ting-Feng Chang
,
Shanq-Jang Ruan
IEEE Trans. Very Large Scale Integr. Syst., 2013

2011
Enhanced Redundant via Insertion with Multi-via Mechanisms.
[BibTeX]
[DOI]
Ting-Feng Chang
,
Tsang-Chi Kan
,
Shih-Hsien Yang
,
Shanq-Jang Ruan
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Nanometer-scale standard cell library for enhanced redundant via1 insertion rate.
[BibTeX]
[DOI]
Tsang-Chi Kan
,
Shih-Hsien Yang
,
Ting-Feng Chang
,
Shanq-Jang Ruan
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011


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