Ting-Ting Y. Lin

According to our database, Ting-Ting Y. Lin authored at least 14 papers between 1992 and 1997.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

1997

The Faulty Behavior of Feedforward Neural Networks with Hard-limiting Activation Fuction.

Zhiyu Tian, Ting-Ting Y. Lin, Shiyuan Yang, Shibai Tong

Neural Comput., 1997

1996

Optimal wire sizing and buffer insertion for low power and a generalized delay model.

John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin

IEEE J. Solid State Circuits, 1996

Simultaneous Routing and Buffer Insertion for High Performance Interconnect.

John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Area Efficient Pipelined Pseudo-Exhaustive Testing with Retiming.

Huoy-Yu Liou, Ting-Ting Y. Lin, Chung-Kuan Cheng

Proceedings of the 33st Conference on Design Automation, 1996

New Performance Driven Routing Techniques With Explicit Area/Delay Tradeoff and Simultaneous Wire Sizing.

John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin, Chin-Yen Ho

Proceedings of the 33st Conference on Design Automation, 1996

1995

Circuit clustering using a stochastic flow injection method.

Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Optimization by iterative improvement: an experimental evaluation on two-way partitioning.

Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Optimization of power dissipation and skew sensitivity in clock buffer synthesis.

Jae W. Chung, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Performance driven multiple-source bus synthesis using buffer insertion.

Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

A general purpose, multiple-way partitioning algorithm.

Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Performability analysis of non-repairable multicomponent systems using order statistics.

Amiya Bhattacharya, Ramesh R. Rao, Ting-Ting Y. Lin

Proceedings of the Sixth IEEE Symposium on Parallel and Distributed Processing, 1994

1993

A New Framework for Designing: Built-in Test Multichip Modules with Pipelined Test Strategy.

Ting-Ting Y. Lin, Huoy-Yu Liou

IEEE Des. Test Comput., 1993

Delay Analysis in Synchronous Circuit-Switched Delta Networks.

Amiya Bhattacharya, Ramesh R. Rao, Ting-Ting Y. Lin

Proceedings of the Seventh International Parallel Processing Symposium, 1993

1992

A probabilistic multicommodity-flow solution to circuit clustering problems.

Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992