Chingwei Yeh

According to our database1, Chingwei Yeh authored at least 45 papers between 1992 and 2017.

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Bibliography

2017
Approximate Distributed Arithmetic for Variable-Latency Table Lookup.
Proceedings of the New Generation of CAS, 2017

2016
Variable-length VLIW encoding for code size reduction in embedded processors.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

A low complexity edge-preserved image compression algorithm for LCD overdrive.
Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

2013
Embedding Repeaters in Silicon IPs for Cross-IP Interconnections.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
Towards Process Variation-Aware Power Gating.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy.
ACM Trans. Archit. Code Optim., 2011

Design of High-Performance CMOS Level Converters Considering PVT Variations.
IEICE Trans. Electron., 2011

RSCE-aware ultra-low-voltage 40-nm CMOS circuits.
Proceedings of the International SoC Design Conference, 2011

Variation-resilient voltage generation for SRAM weak cell testing.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Low power shift registers for megabits CMOS image sensors.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Adaptive Pipeline voltage Scaling in High Performance Microprocessor.
J. Circuits Syst. Comput., 2010

Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays.
IEICE Trans. Electron., 2010

2008
High-Speed and Low-Power Design Techniques for TCAM Macros.
IEEE J. Solid State Circuits, 2008

2007
A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007

2006
Power minimization for dynamic PLAs.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Performance-driven technology mapping with MSG partition and selective gate duplication.
ACM Trans. Design Autom. Electr. Syst., 2006

TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Design of STR level converters for SoCs using the multi-island dual-VDD design technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

An 830mW, 586kbps 1024-bit RSA chip design.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Timing driven power gating.
Proceedings of the 43rd Design Automation Conference, 2006

2005
An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms.
IEEE Trans. Circuits Syst. Video Technol., 2005

A low-power high-SFDR CMOS direct digital frequency synthesizer.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004

2001
Cell-based layout techniques supporting gate-level voltage scaling for low power.
IEEE Trans. Very Large Scale Integr. Syst., 2001

An adaptive path selection method for delay testing.
IEEE Trans. Instrum. Meas., 2001

1999
A simulated annealing based method supporting dual supply voltages in standard cell placement.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A cell selection strategy for low power applications.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Power reduction through iterative gate sizing and voltage scaling.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs.
Proceedings of the 36th Conference on Design Automation, 1999

Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications.
Proceedings of the 36th Conference on Design Automation, 1999

Technnology Mapping for Low Power.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs.
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

1996
On the integration of partitioning and global routing for rectilinear placement problems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995
Circuit clustering using a stochastic flow injection method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Optimization by iterative improvement: an experimental evaluation on two-way partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

On the acceleration of flow-oriented circuit clustering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1994
Block-oriented programmable design with switching network interconnect.
IEEE Trans. Very Large Scale Integr. Syst., 1994

A general purpose, multiple-way partitioning algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1992
A probabilistic multicommodity-flow solution to circuit clustering problems.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992


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