Chingwei Yeh

According to our database, Chingwei Yeh authored at least 53 papers between 1992 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

A 16 nm 140 TOPS/W 5 μJ/Inference Keyword Spotting Engine Based on 1D-BCNN.

Tay-Jyi Lin, Yi-Hsuan Ting, Meng-Ze Hsu, Kuan-Han Lin, Chung-Ming Huang, Fu-Cheng Tsai, Shyh-Shyuan Sheu, Shih-Chieh Chang, Chingwei Yeh, Jinn-Shyan Wang

IEEE Trans. Circuits Syst. II Express Briefs, December, 2023

Force-Sensing Intelligent Vise for Cutting Dynamics Monitoring in Machining.

Po-Han Chen, Tay-Jyi Lin, Chingwei Yeh, Pei-Zen Chang, Wei-Chang Li

Proceedings of the 2023 IEEE SENSORS, Vienna, Austria, October 29 - Nov. 1, 2023, 2023

2022

A 40nm CMOS SoC for Real-Time Dysarthric Voice Conversion of Stroke Patients.

Tay-Jyi Lin, Chen-Zong Liao, You-Jia Hu, Wei-Cheng Hsu, Zheng-Xian Wu, Shao-Yu Wang, Chun-Ming Huang, Ying-Hui Lai, Chingwei Yeh, Jinn-Shyan Wang

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2017

Approximate Distributed Arithmetic for Variable-Latency Table Lookup.

Yi-Hsuan Ting, Tay-Jyi Lin, Cheng-Chun Chang, Chih-Chien Hu, Chingwei Yeh, Jinn-Shyan Wang

Proceedings of the New Generation of CAS, 2017

2016

Variable-length VLIW encoding for code size reduction in embedded processors.

Ting-Yu Shyu, Bo-Yu Su, Tay-Jyi Lin, Chingwei Yeh, Jinn-Shyan Wang, Tien-Fu Chen

Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

A low complexity edge-preserved image compression algorithm for LCD overdrive.

Chao-Yang Chang, Chung-Hsun Huang, Hui-Fu Chen, Chingwei Yeh, Yuan-Sun Chu, Tay-Jyi Lin

Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

2014

Maintaining color fidelity for dual-shot HDR imaging.

Chingwei Yeh, Chen-Yao Tsai, Tay-Jyi Lin, Jiun-In Guo

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2014

2013

Embedding Repeaters in Silicon IPs for Cross-IP Interconnections.

Jinn-Shyan Wang, Keng-Jui Chang, Chingwei Yeh, Shih-Chieh Chang

IEEE Trans. Very Large Scale Integr. Syst., 2013

Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS.

Jian-Shiun Chen, Chingwei Yeh, Jinn-Shyan Wang

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

Towards Process Variation-Aware Power Gating.

Chingwei Yeh, Yuan-Chang Chen, Jinn-Shyan Wang

IEEE Trans. Very Large Scale Integr. Syst., 2012

Complexity-effective Hilbert-Huang transform (HHT) IP for embedded real-time applications.

Shyang-Chyun Chen, Chao-Chuan Chen, Wen-Chi Guo, Tay-Jyi Lin, Ching-Wei Yeh

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Maintaining performance on power gating of microprocessor functional units by using a predictive pre-wakeup strategy.

Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh

ACM Trans. Archit. Code Optim., 2011

Design of High-Performance CMOS Level Converters Considering PVT Variations.

Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh

IEICE Trans. Electron., 2011

RSCE-aware ultra-low-voltage 40-nm CMOS circuits.

Jinn-Shyan Wang, Keng-Jui Chang, Shu-Yi Yang, Tsung-Han Hsieh, Chingwei Yeh

Proceedings of the International SoC Design Conference, 2011

Variation-resilient voltage generation for SRAM weak cell testing.

Chingwei Yeh, Yan-Nan Liu, Jinn-Shyan Wang, Pei-Yao Chang

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

Low power shift registers for megabits CMOS image sensors.

Jinn-Shyan Wang, Tsung-Han Hsieh, Keng-Jui Chang, Chingwei Yeh

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010

Adaptive Pipeline voltage Scaling in High Performance Microprocessor.

Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh

J. Circuits Syst. Comput., 2010

Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays.

Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh

IEICE Trans. Electron., 2010

2008

High-Speed and Low-Power Design Techniques for TCAM Macros.

Chao-Ching Wang, Jinn-Shyan Wang, Chingwei Yeh

IEEE J. Solid State Circuits, 2008

2007

A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS.

Jinn-Shyan Wang, Jian-Shiun Chen, Yi-Ming Wang, Chingwei Yeh

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling.

Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh

Proceedings of the High Performance Embedded Architectures and Compilers, 2007

2006

Power minimization for dynamic PLAs.

Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh

IEEE Trans. Very Large Scale Integr. Syst., 2006

Performance-driven technology mapping with MSG partition and selective gate duplication.

Chi-Shong Wang, Chingwei Yeh

ACM Trans. Design Autom. Electr. Syst., 2006

An AND-type match-line scheme for high-performance energy-efficient content addressable memories.

Hung-Yu Li, Chia-Cheng Chen, Jinn-Shyan Wang, Chingwei Yeh

IEEE J. Solid State Circuits, 2006

TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines.

Jinn-Shyan Wang, Chao-Ching Wang, Chingwei Yeh

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Design of STR level converters for SoCs using the multi-island dual-VDD design technique.

Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications.

Chingwei Yeh, Chao-Ching Wang, Lin-Chi Lee, Jinn-Shyan Wang

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

An 830mW, 586kbps 1024-bit RSA chip design.

Chingwei Yeh, En-Feng Hsu, Kai-Wen Cheng, Jinn-Shyan Wang, Nai-Jen Chang

Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Timing driven power gating.

De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh

Proceedings of the 43rd Design Automation Conference, 2006

2005

An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms.

Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen

IEEE Trans. Circuits Syst. Video Technol., 2005

Design techniques for single-low-V_DD CMOS systems.

Jinn-Shyan Wang, Hung-Yu Li, Chingwei Yeh, Tien-Fu Chen

IEEE J. Solid State Circuits, 2005

A low-power high-SFDR CMOS direct digital frequency synthesizer.

Jinn-Shyan Wang, Shiang-Jiun Lin, Chingwei Yeh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

The CMOS carry-forward adders.

Chung-Hsun Huang, Jinn-Shyan Wang, Chingwei Yeh, Chih-Jen Fang

IEEE J. Solid State Circuits, 2004

Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs.

Jinn-Shyan Wang, Shang-Jyh Shieh, Ching-Wei Yeh, Yuan-Hsun Yeh

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms.

Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Tien-Fu Chen

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding.

Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh

Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004

2001

Cell-based layout techniques supporting gate-level voltage scaling for low power.

Chingwei Yeh, Yin-Shuin Kang

IEEE Trans. Very Large Scale Integr. Syst., 2001

An adaptive path selection method for delay testing.

Wen-Ben Jone, Wu-Sung Yeh, Chingwei Yeh, Sunil R. Das

IEEE Trans. Instrum. Meas., 2001

Analysis and design of high-speed and low-power CMOS PLAs.

Jinn-Shyan Wang, Ching-Rong Chang, Chingwei Yeh

IEEE J. Solid State Circuits, 2001

1999

A simulated annealing based method supporting dual supply voltages in standard cell placement.

Chingwei Yeh, Yin-Shuin Kang

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

A cell selection strategy for low power applications.

Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Power reduction through iterative gate sizing and voltage scaling.

Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs.

Ching-Wei Yeh, Yin-Shuin Kang, Shan-Jih Shieh, Jinn-Shyan Wang

Proceedings of the 36th Conference on Design Automation, 1999

Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications.

Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone

Proceedings of the 36th Conference on Design Automation, 1999

Technnology Mapping for Low Power.

Ching-Wei Yeh, Chin-Chao Chang, Jinn-Shyan Wang

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs.

Ching-Wei Yeh, Min-Cheng Chang, Yin-Shuin Kang

Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999

1996

On the integration of partitioning and global routing for rectilinear placement problems.

Chingwei Yeh, Chi-Shong Wang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995

Circuit clustering using a stochastic flow injection method.

Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Optimization by iterative improvement: an experimental evaluation on two-way partitioning.

Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

On the acceleration of flow-oriented circuit clustering.

Ching-Wei Yeh

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1994

Block-oriented programmable design with switching network interconnect.

Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel

IEEE Trans. Very Large Scale Integr. Syst., 1994

A general purpose, multiple-way partitioning algorithm.

Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

1992

A probabilistic multicommodity-flow solution to circuit clustering problems.

Ching-Wei Yeh, Chung-Kuan Cheng, Ting-Ting Y. Lin

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992