Tirumalarao Kadiyam

According to our database, Tirumalarao Kadiyam authored at least 2 papers between 2024 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

FeSATLock: An Energy Efficient and SAT Attack Resilient Logic Locking Design With FeFET LUT Architecture for Enhanced Hardware Security.

Tirumalarao Kadiyam, Venu Birudu, Aditya Japa, Fadi N. Sibai, Venkateswarlu Gonuguntla, Ramesh Vaddi

IEEE Access, 2025

2024

Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices.

Venu Birudu, Tirumalarao Kadiyam, Koteswararao Penumalli, Aditya Japa, Sushma Nirmala Sambatur, Chongyan Gu, Siva Sankar Yellampalli, Ramesh Vaddi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024