Ramesh Vaddi
Orcid: 0000-0003-3158-4013
According to our database1,
Ramesh Vaddi
authored at least 33 papers
between 2009 and 2023.
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Bibliography
2023
A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks.
Microelectron. J., September, 2023
Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design.
Microelectron. J., March, 2023
2022
Microelectron. J., 2022
Chest X ray and cough sample based deep learning framework for accurate diagnosis of COVID-19.
Comput. Electr. Eng., 2022
Design and Exploration of Negative Capacitance FETs for Energy Efficient SRAM based In-Memory XNOR/Input and Weight Product Operation for Deep Neural Networks.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
2021
Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things.
Int. J. Circuit Theory Appl., 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
Design and Analysis of 4-bit and 5-bit Flash ADC's in 90nm CMOS Technology for Energy Efficient IoT Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
2020
Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage.
Int. J. Circuit Theory Appl., 2020
Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator.
IET Circuits Devices Syst., 2020
A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks.
IET Circuits Devices Syst., 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD.
J. Circuits Syst. Comput., 2018
A Low-power Low-noise Open-loop Configured Signal Folding Neural Recording Amplifier.
Proceedings of the International SoC Design Conference, 2018
Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Low Write Energy STT-MRAM Cell Using 2T- Hybrid Tunnel FETs Exploiting the Steep Slope and Ambipolar Characteristics.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017
A low voltage capacitor based current controlled sense amplifier for input offset compensation.
Proceedings of the International SoC Design Conference, 2017
Energy efficient and high throughput transceiver design in the capacitive coupling mode exploring tunnel transistors for 3D ICs.
Proceedings of the International SoC Design Conference, 2017
Tunneling Field Effect Transistors for Energy Efficient Logic, Sensor Interface and 3D IC Circuits for IoT Platforms.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2017
2016
Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction.
IET Circuits Devices Syst., 2016
Circuit and Architectural Co-design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
2014
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
2011
Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options.
Microelectron. J., 2011
Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
2010
Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic.
Microelectron. J., 2010
Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs.
J. Low Power Electron., 2010
Comparison of nano-scale complementary metal-oxide semiconductor and 3T-4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic.
IET Circuits Devices Syst., 2010
2009
Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications.
VLSI Design, 2009