Titu Mary Ignatius

Orcid: 0000-0001-7794-653X

According to our database1, Titu Mary Ignatius authored at least 5 papers between 2024 and 2025.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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Bibliography

2025
Boosting AES Intrinsic Resilience Using Split SubBytes Round Function Against Power Attacks.
IEEE Embed. Syst. Lett., February, 2025

RAESC: A Reconfigurable AES Countermeasure Architecture for RISC-V With Enhanced Power Side-Channel Resilience.
IEEE Comput. Archit. Lett., 2025

2024
Improvement in Resilience of AES Design With Reconfigured CFB Mode Against Power Attacks.
IEEE Trans. Very Large Scale Integr. Syst., November, 2024

Power Side-Channel Attacks on Crypto-Core Based on RISC-V ISA for High-Security Applications.
IEEE Access, 2024

Impact of Pipelining on Low Power IoT applicable RISC-V ISA Core Micro-architectures.
Proceedings of the 17th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2024


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